Data bus apparatus and control method for effectively compensating fault signal line
A data bus and fault signal technology, which is applied to the redundancy of hardware for data error detection, electrical digital data processing, and response error generation. It can solve the problem that 32 signal lines are invalid, inefficient, and cannot be used to transmit data. And other issues
Inactive Publication Date: 2003-06-11
SAMSUNG ELECTRONICS CO LTD
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[0006] However, the main disadvantage of the Olarig US Patent Application 2002 / 0099980 system is that if there is a single faulty signal line on both the upper and lower 32-bit buses that make up the 64-bit bus, the entire 64-bit data bus cannot be used to transfer data
Therefore, only two faulty signal lines on the 64-bit bus of Olarig's 2002 / 0099980 can render the entire 64-bit bus of Olarig's 2002 / 0099980 unusable
Another shortcoming of Olarig's 2002 / 0099980 system: a single faulty signal line in Olarig's 2002 / 0099980 invalidated 32 signal lines, forcing the data to be transmitted to be transmitted on a 32-bit bus instead of a 64-bit bus transmission
it's so inefficient
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[0022] One solution to overcome the problem of possible faulty signal lines is to provide two buses for transferring data. Each bus includes a plurality of signal lines. figure 1 Such an arrangement where there are two buses in an Asynchronous Transfer Mode ATM cell is described. Connected to both buses 10 and 20 are m modules, each with a BIU. Data bus 10 is called the main data bus and data bus 20 is called the substitute data bus. When there is no faulty signal line, the data bus 10 is only used to transfer data and the replacement bus 20 is idle. When a faulty signal line is detected in the main data bus 10, the alternate bus 20 is used to transfer data while the main bus remains free.
[0023] In order for this device to work in an ATM unit, each of the m modules 30-1 to 30-m must have two BIUs, the first BIU 40 being connected to the main bus 10 and the second BIU 50 being connected to the main bus 10. Alternative bus 20 connection. Therefore, when the main bus 10 i...
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The present invention discloses a data bus connecting individual modules and carrying data there between. The data bus includes primary signal lines and supplementary signal lines. A master module having a bus monitor and a microprocessor detects for faulty signal lines and substitutes supplementary signal lines for faulty primary signal lines enabling the bus to continue carrying data between modules connected thereto. The status of the signal lines are communicated to all the other modules on the bus by a special signal line on the bus so that each module is informed of the substitution.
Description
[0001] priority claim [0002] The present application claims the priority of my patent application filed with the Korean Intellectual Property Office on November 29, 2001, assigned application number 2001-75072 and titled "Data Bus System and Control Method". Its content will be combined here as a reference. technical field [0003] The present invention relates to a data bus system, and more particularly, the present invention relates to a data bus having only a single bus with additional signal lines for compensating for faulty, erroneous signal lines. technical background [0004] In a data bus system using a single data bus with multiple signal lines, when one or more of the multiple signal lines fails, the data bus often cannot function properly. [0005] Olarig's US Patent Application No. 2002 / 0099980A1 seeks to overcome this problem using a 64-bit bus. In US Patent Application 2002 / 0099980 to Olarig, the 64-bit bus consists of a 32-bit low bus and a 32-bit high bus...
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IPC IPC(8): G06F13/40G06F11/20
CPCG06F11/2007G06F13/40
Inventor 曹永洙
Owner SAMSUNG ELECTRONICS CO LTD