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Asynchronous decade counter IC

A technology of integrated circuits and counters, applied in asynchronous pulse counters, pulse counters, counting chain pulse counters, etc., can solve problems such as lack of logic functions

Inactive Publication Date: 2010-05-05
HEBEI NORMAL UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This counter has the following disadvantages: (1) it does not have the ability to make Q 3 Q 2 Q 1 Q 0 The logic function of directly setting 0000 and setting 1001

Method used

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  • Asynchronous decade counter IC
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  • Asynchronous decade counter IC

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Embodiment Construction

[0018] Depend on figure 1 , 2 As can be seen from the shown embodiment, it is made up of a 1-bit binary counter and an asynchronous pentary counter; the described 1-bit binary counter is composed of the first JK flip-flop FF 0 , the first "NAND gate" RF with two 0-set input terminals, the second "NAND gate" SF with two 1-set input terminals, the first JK flip-flop FF 0 The R terminal is connected to the output terminal of the first "NAND gate" RF, and the first JK flip-flop FF 0 The S terminal is connected to the output terminal of the second "NAND gate" SF, and the first JK flip-flop FF 0 The clock input terminal of the CP 0 , and its two output terminals are respectively the first output terminal Q 0 and the second output Q 0 ; The asynchronous five-ary counter consists of the second to fourth JK flip-flops FF 1 -FF 3 , the first "NAND gate" RF with two 0 input terminals, the second "NAND gate" SF with two 1 input terminals, and the second JK flip-flop FF 1 and the f...

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Abstract

The invention relates to a asynchronous decade counter integrated circuit, which is improved on the base of present 74LS290 chip. The main improved points comprise: (1) changing the 'OR gate' of the Rends of the second and the third JK triggers as FF1 and FF2 of the logic circuit map of present 74LS290 chip into 'AND gate'; keeping the 'S' ends of the logic circuit map of the second and third JKtriggers of present 74LS290 in high voltage or hung. The advantages of said invention comprise: the invention not only has the function of binary-quinary-decade counter of former 74LS290 chip, but also has the logic function of presetting 0001 and 1001 accurately; and the functions of inventive integrated circuit has rigorous logic theory relation.

Description

technical field [0001] The invention relates to an asynchronous decimal counter integrated circuit, which belongs to the MSI digital circuit integrated chip. Background technique [0002] At present, the most commonly used asynchronous decade counter (ie 74LS290) is composed of a 1-bit binary counter and an asynchronous five-ary counter. This counter has the following disadvantages: (1) it does not have the ability to make Q 3 Q 2 Q 1 Q 0 The logic function of directly setting 0000 and setting 1001. (2) S appears in its function table 01 ·S 02 = 0, R 01 · R 02 =0 logic state, which is absolutely not allowed in logic theory. Contents of the invention [0003] The technical problem to be solved by the present invention is to overcome the shortcomings of the existing 74LS290 chip, and provide an asynchronous decimal counter integrated circuit with complete logic functions and strict logic theory. [0004] The technical solution adopted by the present invention to so...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K23/66H03K23/72H03K23/58G06F7/60
Inventor 李秀群范力宁
Owner HEBEI NORMAL UNIV
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