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Asynchronous decade counter IC

A technology of integrated circuits and counters, applied in asynchronous pulse counters, pulse counters, counting chain pulse counters, etc., can solve problems such as lack of logic functions

Inactive Publication Date: 2006-02-22
HEBEI NORMAL UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This counter has the following disadvantages: (1) it does not have the ability to make Q 3 Q 2 Q 1 Q 0 The logic function of directly setting 0000 and setting 1001

Method used

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  • Asynchronous decade counter IC
  • Asynchronous decade counter IC
  • Asynchronous decade counter IC

Examples

Experimental program
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Embodiment Construction

[0018] Depend on figure 1 , 2 The embodiment shown shows that it consists of a 1-bit binary counter and an asynchronous pentary counter; a 1-bit binary counter consists of a JK flip-flop FF 0 , "NAND gate" RF with two 0 input terminals, "NAND gate" SF with two 1 input terminals, JK flip-flop FF 0 The R terminal is connected to the output terminal of the "NAND gate" RF, and the JK flip-flop FF 0 The S terminal is connected to the output terminal of the "NAND gate" SF, and the JK flip-flop FF 0 The clock input terminal of the CP 0 , whose two outputs are Q 0 and Q 0 ; An asynchronous pentary counter is controlled by JK flip-flop FF 1 -FF 3 , "NAND gate" RF with two 0 input terminals, "NAND gate" SF with two 1 input terminals, JK flip-flop FF 1 and FF 3 The clock input terminal of the CP 1 , JK flip-flop FF 2 The clock input terminal of the JK flip-flop FF 1 The output Q 1 , JK flip-flop FF 3 The S terminal is connected to the output terminal of the "NAND gate" SF, ...

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Abstract

The invention relates to a asynchronous decade counter integrated circuit, which is improved on the base of present 74LS290 chip. The main improved points comprise: (1) changing the 'OR gate' of the R ends of the second and the third JK triggers as FF1 and FF2 of the logic circuit map of present 74LS290 chip into 'AND gate'; keeping the 'S' ends of the logic circuit map of the second and third JK triggers of present 74LS290 in high voltage or hung. The advantages of said invention comprise: the invention not only has the function of binary-quinary-decade counter of former 74LS290 chip, but also has the logic function of presetting 0001 and 1001 accurately; and the functions of inventive integrated circuit has rigorous logic theory relation.

Description

technical field [0001] The invention relates to an asynchronous decimal counter integrated circuit, which belongs to the MSI digital circuit integrated chip. Background technique [0002] At present, the most commonly used asynchronous decade counter (ie 74LS290) is composed of a 1-bit binary counter and an asynchronous five-ary counter. This counter has the following disadvantages: (1) it does not have the ability to make Q 3 Q 2 Q 1 Q 0 The logic function of directly setting 0000 and setting 1001. (2) It appears in the menu S 01 · S 02 ‾ = 0 , R 01 · R 02 ‾ = 0 The logical state of...

Claims

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Application Information

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IPC IPC(8): H03K23/66H03K23/72H03K23/58G06F7/60
Inventor 李秀群范力宁
Owner HEBEI NORMAL UNIV
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