Inter-sequence permutation turbo code system and operation methods thereof

a turbo code system and sequence permutation technology, applied in the field of turbo code systems, can solve the problems of large memory space for the temporary received samples, memory usage, and the inability to decode more than ten sequences at the same time, and achieve the effect of improving the performance of tcs

Inactive Publication Date: 2007-01-11
IND TECH RES INST
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  • Abstract
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Benefits of technology

[0007] Cooperative decoding can improve performance of TCS with short codeword length. Besides, conventional A Posteriori Probability (APP) decoding modules and interleaving techniques can be applied and the feature of “Backward Compatible” is attainable. More than one schedulers can be applied for scheduling of cycles of APP decoding (or called APP decoding runs) or memory releasing.

Problems solved by technology

Memory usage would be the most critical implementation problem for the cooperative TCS.
Decoding more than ten sequences at the same time requires large memory space for the temporary received samples.

Method used

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  • Inter-sequence permutation turbo code system and operation methods thereof
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  • Inter-sequence permutation turbo code system and operation methods thereof

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Embodiment Construction

[0024] The details to the exemplary embodiments of the invention will be described as follows and the same reference numbers are used throughout the drawings to refer to the same or like parts.

[0025] As stated above, ISP is a concept permuting between different sequences, which is easy to be comprehended for persons skilled in the art. For ease of understanding, we can take the sequences as matrices. One element in one matrix, if it is to be permuted, will be moved to one coordinate in the same or another matrix with the ordinal number within a span prior or successive to the element. In the present invention, preferably, one sequence is to be inter-sequence permuted with two other sequences which are consecutively before and after the sequence to be permuted. One exemplary procedure of ISP is given in FIG. 1, wherein i is ordinal number of sequences, R and P are ordinal numbers of matrices, m and n are ordinal numbers of elements in the R-th and P-th matrices, where 0≦m,n[0026] st...

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Abstract

A high performance real-time turbo code system is proposed. The proposed system exploits cooperative coding architecture and a proper decoding scheduling to achieve low error rate within a constrained latency. Permutation schemes and hardware embodiments utilizing the cooperative coding are also shown. Various memory saving techniques are provided to reduce memory usage in both encoder and decoder. The proposed system is compatible with 3rd generation mobile standards and cost of designing new parts exclusively for the proposed system can be minimized. This invention can provide substantial coding and system capacity gains for real-time applications in a wireless environment.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a turbo code system, more specifically, a turbo code system utilizing cooperative coding architecture and a proper decoding scheduling to achieve high performance real-time encoding and decoding. [0003] 2. Description of Related Art [0004] Turbo Code (TC) was invented in 1993, which renders extraordinary, near Shannon limit performance by applying the iterative decoding algorithm. Following researches on the area of Forward Error-Control (FEC) were inspired from this primitive code structure and decoding algorithm. We shall thus refer to any FEC system that utilizes the so-called “Turbo Principle” in decoding as a Turbo Code System (TCS). [0005] Codeword length influences the performance of TCS. TCS with long codeword length performs excellently but decoder of the TCS has large decoding latency and hardware complexity. Moreover, the decoder requires considerable number of iterations ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H03M13/05
CPCH03M13/2771H03M13/6561H03M13/2987
Inventor ZHENG, YAN-XIUSU, YU-TED
Owner IND TECH RES INST
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