Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

Active Publication Date: 2012-08-16
STATS CHIPPAC LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0022]A need exists to minimize escape pitch of trace lines for higher routing density. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor die having a plurality of bumps formed over a surface of the semiconductor die, providing a substrate, forming a plurality of conductive traces over a surface of the substrate with interconnect sites, and forming a masking layer over the surface of the substrate. The masking layer has a plurality of parallel elongate

Problems solved by technology

Multiple layer substrates are expensive and, in conventional flipchip constructs, the substrate alone typically accounts for more than half the package cost.
The high cost of multilayer substrates has been a factor in limiting proliferation of flipchip technology in mainstream products.
The escape routing pattern typically introduces additional electrical parasitics because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path.
Electrical parasitics can significantly limit package performance.
In such processes, the melted solder may flow from the interconnect site along the metal of the circuitry, depleting the solder at the connection site and, where the bumps are collapsible under reflow conditions, the bumps may contact adjacent circuitry or nearby bumps, resulting in electrical failure.
Process limitations in patterning the solder mask prevent reliably forming well-aligned and con

Method used

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  • Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings
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  • Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

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DETAILED DESCRIPTION OF THE DRAWINGS

[0048]The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as can be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.

[0049]Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to f...

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Abstract

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Description

CLAIM TO DOMESTIC PRIORITY[0001]The present application is a continuation-in-part of U.S. patent application Ser. No. 12 / 362,627, filed Jan. 30, 2009, and claims priority to the foregoing parent application pursuant to 35 U.S.C. ยง 120.FIELD OF THE INVENTION[0002]The present invention relates to semiconductor devices and, particularly, to a semiconductor device and method of forming narrow interconnect sites on a substrate with elongated mask openings.BACKGROUND OF THE INVENTION[0003]Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integ...

Claims

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Application Information

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IPC IPC(8): H01L21/56H01L23/498
CPCH01L21/563H01L24/13H01L24/16H01L24/32H01L24/48H01L24/81H01L2224/1308H01L2224/13082H01L2224/131H01L2224/13111H01L2224/13116H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/16013H01L2224/16014H01L2224/16225H01L2224/16237H01L2224/27013H01L2224/32145H01L2224/48091H01L2224/73203H01L2224/73265H01L2224/81097H01L2224/81191H01L2224/81208H01L2224/8121H01L2224/81815H01L2224/83051H01L2224/83192H01L2924/01013H01L2924/01015H01L2924/01027H01L2924/01029H01L2924/01046H01L2924/01047H01L2924/01049H01L2924/0105H01L2924/01074H01L2924/01075H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/01322H01L2924/13091H01L2924/14H01L2924/1433H01L2924/19041H05K3/3452H05K2201/0989H05K2201/10674H01L2924/0132H01L24/29H01L2924/00013H01L2924/01006H01L2924/01033H01L2924/014H01L2924/0133H01L2224/29109H01L2224/29111H01L2224/48227H01L2224/2919H01L2224/11822H01L2224/13109H01L2224/73204H01L2924/12041H01L2924/15311H01L2924/1306H01L2224/16235H01L2924/00014H01L2224/13099H01L2924/00H01L2924/00012H01L2924/0665H01L24/73H01L2224/05111H01L2224/05124H01L2224/05139H01L2224/05144H01L2224/05147H01L2224/05155H01L2224/05611H01L2224/05624H01L2224/05639H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/13023H01L2924/15174H01L2924/181H01L2224/45099H01L2224/45015H01L2924/207
InventorPENDSE, RAJENDRA D.
OwnerSTATS CHIPPAC LTD