Self-correction precursor 0/1 predicting unit for floating-point adder

Abstract

The invention relates to a self-correction precursor 0 / 1 predicting method for a floating-point adder, which adopts the combination method of a multiple-input logical gate and parallel computation to realize an output result as a final correct result, and the output result has no need to be corrected by depending on an adder; the parallel computation is adopted, for example, the operand bit wide is increased, and the critical path length can not be influenced. When the floating-point add is computed, the displacement time and index regulating information needed by the normalization of a computation result is synchronously predicted, a predicting result is not output by the adder but is generated by the predicting unit and is a corrected value which has no need to be further corrected, andthe critical path of the predicting unit can not be lengthened along with lengthening the bit wide of an operand.

Description

technical field

[0001] The invention relates to a leading 0 / 1 prediction method, in particular to a self-correcting leading 0 / 1 prediction method for a floating-point adder. Background technique

[0002] The document "G. Zhang, W. Hu, Z. Qi, "Parallel error detection for leading zero anticipation". Journal of Computer Science and Technology, v 21, n 6, p 901-906, November 2006." proposed a parallel The leading 0, 1 prediction unit error correction technology that can realize error correction without relying on the carry signal of the adder is realized. The main idea is to use "positive tree" and "negative tree" to compress the results of "positive encoding" and "negative encoding", and finally output the correct result through OR logic. Its unique tree-like compression structure makes the "encoding" signal have to pass through a series of logic gates before finally reaching the output terminal. In this hierarchical tree-like structure, the length of the key path is determin...

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