Dual Gate Field Effect Transistor

Abstract

The present invention provides a double gate field effect transistor, comprising: a device layer, the device layer has opposite first and second surfaces; a source and a drain located in the device layer, isolated from each other and having different conductivity types and a channel region between the source and the drain; the channel region sequentially includes a first pocket injection region, a source connection region and a second pocket injection region along the first surface of the device layer to the second surface; the first pocket injection region 1. The second pocket injection regions are all electrically connected to the drain, and the source connection region is electrically connected to the source; the first gate structure located on the first surface of the device layer corresponding to the position of the first pocket injection region; located on the device A second gate structure corresponding to the position of the second pocket injection region on the second surface of the layer. The double-gate field-effect transistor of the present invention has high response speed and sensitive switching characteristics, and meets the requirement of reducing energy consumption after devices with small size are scaled down, and avoids a series of secondary effects.

Description

technical field [0001] The invention relates to a field effect transistor, in particular to a double gate field effect transistor. Background technique [0002] In the development process of semiconductor VLSI, under the guidance of scaling of CMOS devices, the density and performance of transistors have been continuously and systematically increased following Moore's law. However, when the semiconductor industry develops to the 45nm node or smaller, the power consumption and power consumption density of chips have gradually become a problem that needs to be solved urgently. The power supply voltage has maintained 5V as the standard for all levels of technology for a long time. Therefore, scaling down the external voltage source (VDD-scaling) has increasingly become a bottleneck restricting the development of metal oxide field effect transistors (MOSFETs). [0003] At present, it has been proposed that the use of gate bias in metal-oxide field-effect transistors can induce...

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