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Wafer and a method of dicing a wafer

A wafer and chip technology, applied in the field of sharply reducing the scribe width of silicon semiconductor wafers, can solve the problems of reducing the scribe width, inability to apply metallization patterns, and reducing the production volume of etching tools

Inactive Publication Date: 2012-02-15
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The conventional method to realize the reduction of scribe line width adopts the repetitive plasma dry etching method, however, said repetitive plasma dry etching method cannot be applied to copper-based, double damascene, metallized patterns because copper cannot be etched by plasma. eclipse
Furthermore, conventional methods use many and long overetch times, whereby the time required results in significantly reduced etch tool throughput
However, there is no solution that can be used to drastically reduce the scribe line width in the case of complex integrated circuits

Method used

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Embodiment Construction

[0025] Typically, when manufacturing semiconductor devices (chips) on a wafer, such as a silicon wafer of a semiconductor wafer, dicing streets are formed for sawing the semiconductor wafer during final assembly and packaging / sealing stages. Such dicing streets, which encompass each chip on the wafer on each side of the chip (eg, four sides if the chip is rectangular), include varying widths from technology to technology. The cutting tracks are also referred to as scribe lines or kerfs. Narrow available cuts or scribes using conventional techniques include, for example, widths of about 62 μm.

[0026] Scribing or notching defines the minimum distance between chips required by the dicing technique used and additionally accommodates a large number of structures used to control the manufacturing process. Such structures are, for example, typical process control monitoring test structures (PCMs), photolithographic alignment structures, wafer level reliability test circuits, film ...

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Abstract

The invention relates to a wafer and a method of dicing a wafer. The wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.

Description

technical field [0001] Embodiments of the present invention relate to wafers and methods of dicing wafers, and in particular to methods of drastically reducing the width of scribe lines of silicon semiconductor wafers. This is especially required in modern chip production in order to maximize the utilization of the silicon of a semiconductor wafer so that the wafer can accommodate the largest possible number of chips. This is especially relevant for fast or sensitive power products, logic products, memory products, and the like. Background technique [0002] Typically, when manufacturing semiconductor devices (chips) on a wafer, such as a silicon wafer of a semiconductor wafer, dicing streets are formed for sawing the semiconductor wafer during final assembly and packaging / sealing stages. Such dicing streets, which encompass each chip on the wafer on each side of the chip (eg, four sides if the chip is rectangular), include varying widths from technology to technology. The...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544H01L23/58H01L21/78G03F7/20
CPCG03F7/70625G03F7/70683G03F9/7084H01L21/78H01L22/34H01L23/544H01L23/562H01L23/585H01L2223/5446H01L2223/54466H01L2924/0002H01L2924/00
Inventor J.巴斯卡兰G.米科利F.斯特芬A.瓦特
Owner INFINEON TECH AG