Data processing method and device for 10 gigabit media independent interface (XGMII) and inter-chip bidirectional handshaking method

Abstract

The invention discloses a data processing method and a data processing device for a 10 gigabit media independent interface (XGMII) and an inter-chip bidirectional handshaking method. The data processing method for the XGMII comprises the following steps of: configuring a standard data byte sequence; and analyzing a data byte sequence of the received single data rate XGMII data, comparing with the standard data byte sequence, and adjusting the data byte sequence of the received single data rate XGMII data to form the standard data byte sequence. By adjusting the data byte sequence of the received single data rate XGMII data to form the standard data byte sequence, the problem of possible uncertain dislocation of data communication of different XGMII extender sublayers (XGXS) among chips is solved, so that the general applicability of communication among the chips is ensured, and the transmission reliability of initialized data among the chips is ensured through a bidirectional handshaking function of the chips.

Description

technical field [0001] The invention relates to an XGMII interface data processing method and device and a two-way handshaking method between XGMII interface chips realized by the device. Background technique [0002] 10Gbit Ethernet technology is widely used in high-speed transmission due to its advantages of high speed, flexibility and controllability. Among them, XGMII is a full-duplex interface between the media access control (Media Access Control, MAC) layer and the physical layer (Physical layer, PHY) of 10G Ethernet, and is a bridge connecting the Ethernet data link layer and the physical layer. XGMII is an independent interface between the Reconciliation Sublayer (RS) and the Physical Coding Sublayer (PCS), which enables data transmission between the two layers at a rate of 10Gbit / s. [0003] The purpose of XGMI I is to provide a stable, reliable, and clear interconnection between the MAC layer and the PHY. Its function is similar to the medium independent interfac...

AI Technical Summary

Problems solved by technology

However, in actual applications, it is found that when the sampling receiving clock is recovered during the splicing process, the data will have a phase deviation, which will lead to the separation of interface data sampling, which will result in the process of splicing two 32bits data into one 64bits data. The two 32bits data are separated so that they cannot be spliced ​​into the same 64bits data, but are spliced ​​into two 64bits data separately, and different IP COREs implement different channel data width conversion definitions, which leads to inconsistent data order of this interface. Through sampling It also counts the data misalignment of two types of IP CORE interfaces, and analyzes as follows: image 3 The situation shown: 8 8-bit binary data, that is, the 64bits data of the sending end is compared with the 8 8-bit binary data spliced ​​and restored by the XGMII interface of the receiving end (IP CORE-A or IP CORE-B), and the data byte is found There is an obvious dislocation in the sequence, which is caused by the different definitions of the implementation channel data width in different IP CORE

Therefore, due to the uncertainty of data misalignment in the reception of data on this interface, more additional processing is required when receiving

At the same time, during the initial data transmission process between chips, due to the difference in the reset time of the two chips, that is, the reset mechanism is different, it will cause initial data reception errors during the data transmission process.

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