Data interleaving method and device
A data and interleaver technology, applied in the field of data interleaving methods and devices, to achieve the effect of improving interleaving performance
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Embodiment 1
[0020] In Embodiment 1, take the code multiplexing process of HS-DSCH modulated by 16QAM as an example, in this process, two interleavers of the same size are used to interleave the input bits, and the two interleavers are both R2× C2=32×30, the input bit is divided into two-way bit sequences between the two interleavers, and the bit u p，k and u p，k+1 sent to the first interleaver, bit u p，k+2 and u p，k+3 Sent to the second interleaver, the output bit sequences of the two interleavers are combined in pairs according to the order of allocation, specifically, bit v p，k and v p，k+1 output from the first interleaver, while bit v p，k+2 and v p，k+3 It is output from the second interleaver, where k mod4=1, and so on for subsequent bit sequences.
[0021] In Embodiment 1, different interleaving patterns are respectively configured for the two interleavers, wherein each interleaving pattern is defined as an example where only the initial position of the input bit sequence is defi...
Embodiment 2
[0053] In the second embodiment, the code multiplexing process of HS-DSCH modulated by 64QAM is taken as an example. In this process, three interleavers of the same size are used to interleave the input bits, and the three interleavers are all R2× C2=32×30, the input bits are divided into three-way sequences between the three interleavers, bit u p，k and u p，k+1 sent to the first interleaver, bit u p，k+2 and u p，k+3 sent to the second interleaver, bit u p，k+4 and u p，k+5 Sent to the third interleaver, the sequences of each channel are interleaved separately, and the output bit sequences of the three interleavers are combined according to the order of allocation, specifically, bit v p，k and v p，k+1 Output from the first interleaver, bit v p，k+2 and v p，k+3 Output from the second interleaver, bit v p，k+4 and v p，k+5 Output from the first interleaver, and so on for subsequent bit sequences.
[0054] In the second embodiment, as long as it is ensured that the interleaving...
Embodiment 3
[0057] In the third embodiment, taking the E-DCH modulated by 4PAM as an example, in this process, two identical interleavers with a size of R2x30 are used, wherein R2 satisfies The smallest integer of . The input bits enter the two-way interleaver in turn. u p，k Enter the first interleaver, u p，k+1 Enter the second interleaver. After the interleaving of the two-way interleaver, the bits are read out from the two interleavers in turn for output, that is, v p，k from the first interleaver, v p，k+1 From the second interleaver with k mod 2=1. For example, a bit sequence with a length of 60, its index is: 1, 2, ..., 60, then the index is {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59} enter the first interleaver, Indexes are {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48 , 50, 52, 54, 56, 58, 60} bits enter the second interleaver.
[0058] If the two interleave...
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