A double polycrystalline soi strained sige channel bicmos integrated device and its preparation method
An integrated device, dual polycrystalline technology, applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve problems such as threshold voltage drift, device size cannot be further reduced, and large impact.
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Embodiment 1
[0127] Embodiment 1: The preparation of a self-aligned double polycrystalline SOI, strained SiGe back channel BiCMOS integrated device and circuit with a conductive channel of 45nm, the specific steps are as follows:
[0128] Step 1, epitaxial growth.
[0129] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;
[0130] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 .
[0131] Step 2, the implementation method of isolation area preparation is:
[0132] (2a) Deposit a layer of SiO with a thickness of 500nm on the surface of the epitaxial Si layer at 800°C by ch...
Embodiment 2
[0200] Embodiment 2: The preparation of a self-aligned double polycrystalline SOI, strained SiGe back channel BiCMOS integrated device and circuit with a conductive channel of 30nm, the specific steps are as follows:
[0201] Step 1, epitaxial growth.
[0202] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 300nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;
[0203] (1b) Using chemical vapor deposition (CVD), grow an N-type epitaxial Si layer with a thickness of 80nm on the upper Si material at 700°C as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 .
[0204] Step 2, isolation area preparation.
[0205] (2a) Deposit a layer of SiO with a thickness of 400nm on the surface of the epitaxial Si layer at 700°C by chemical vapor deposition (CVD). 2 Floor;
[0206] (2b) In the ph...
Embodiment 3
[0273] Embodiment 3: The preparation of a self-aligned double polycrystalline SOI, strained SiGe back channel BiCMOS integrated device and circuit with a conductive channel of 22nm, the specific steps are as follows:
[0274] Step 1, epitaxial growth.
[0275] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 150nm, and the upper material is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;
[0276] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 50nm on the upper Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 .
[0277] Step 2, isolation area preparation.
[0278] (2a) Deposit a layer of SiO with a thickness of 300nm on the surface of the epitaxial Si layer at 600°C by chemical vapor deposition (CVD). 2 Floor;
[0279] (2b) ...
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