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Driving circuit, array substrate and display device

A technology for driving circuits and array substrates, which is applied in the fields of driving circuits, array substrates, and display devices. It can solve problems such as sequential output waveform mismatch, large glass impedance, and control signal delay, and achieve the effect of avoiding excessive substrate impedance.

Active Publication Date: 2012-11-21
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of this, the present invention provides a driving circuit, an array substrate, and a display device, which can solve the problem of delay in receiving control signals received by multiple series-connected gate drivers due to the high impedance of the substrate glass of the array substrate in the prior art. As a result, the sequential output waveforms of different gate driver outputs do not match.

Method used

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  • Driving circuit, array substrate and display device
  • Driving circuit, array substrate and display device
  • Driving circuit, array substrate and display device

Examples

Experimental program
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Effect test

Embodiment 1

[0032] Such as figure 2 Shown is a schematic structural diagram of a driving circuit according to Embodiment 1 of the present invention. The driving circuit is applied to an array substrate. The driving circuit includes: a timing controller 201 and two gate drivers (a gate driver 202a and a gate driver 202b). ), the timing controller 201 and the gate driver 202a close to the timing controller 201 are directly connected through a timing control signal transmission line 203a and a timing control signal transmission line 203b. The gate drivers 202b of the driver 201 are directly connected through a timing control signal transmission line 203c and a timing control signal transmission line 203d, that is, the timing controller 201 and the two gate drivers are directly connected through a timing control signal transmission line respectively. In this embodiment, the gate driver 202a is a first gate driver, and the gate driver 202b is a second gate driver

[0033] From figure 2 It can b...

Embodiment 2

[0037] Such as image 3 Shown is a schematic structural diagram of the driving circuit of the second embodiment of the present invention. The driving circuit is applied to an array substrate. The driving circuit includes: a timing controller 201 and three gate drivers (gate driver 202a, gate driver 202b). And the gate driver 202c), the timing controller 201 and the gate driver 202a (ie, the first gate driver) close to the timing controller 201 are directly connected through a timing control signal transmission line 203a and a timing control signal transmission line 203b The timing controller 201 and the gate driver 202b farthest from the timing controller 201 are directly connected through a timing control signal transmission line 203c and a timing control signal transmission line 203d, and the gate driver 202c in the middle position is directly connected to the The gate driver 202a is connected in series through the timing control signal transmission line 203e and the timing co...

Embodiment 3

[0045] The setting method of the STV signal transmission line can be the same as the above timing signal transmission line.

[0046] Such as Figure 4 Shown is a schematic diagram of the structure of the driving circuit in the third embodiment of the present invention. The driving circuit in this embodiment is similar to figure 2 The difference between the driving circuit in the first embodiment shown is that it further includes: a first frame start signal line. The first frame start signal line includes an STV signal transmission line 204a and an STV signal transmission line 204b. The timing controller 201 and In addition to the direct connection between the gate drivers 202a through the timing control signal lines 203a and 203b, they are also directly connected through the STV signal transmission line 204a. The timing controller 201 and the gate driver 202b are directly connected through the timing control signal lines 203c and 203d. In addition to the connection, it is also di...

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PUM

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Abstract

The invention provides a driving circuit, an array substrate and a display device. The driving circuit comprises a time schedule controller and a plurality of grid drivers, wherein the time schedule controller is directly connected with a first grid driver through a time schedule control signal transmission line; in the grid drivers, the first grid driver is closest to the time schedule controller; and the time schedule controller is also directly connected with at least one second grid driver except the first grid driver in the grid drivers through the time schedule control signal transmission line. In the driving circuit, the time schedule controller is directly connected with the grid drivers through the time schedule control signal transmission line, and the time schedule control signals transmitted to the grid drivers by the time schedule controller are differently controlled, so that the delay problem of the control signals received by the grid drivers caused by too big impedance of panel glass of a liquid crystal array substrate is effectively avoided.

Description

Technical field [0001] The present invention relates to the field of display technology, in particular to a driving circuit, an array substrate and a display device. Background technique [0002] Such as figure 1 Shown is a schematic structural diagram of a driving circuit for an array substrate in the prior art. The driving circuit includes: a timing controller (TCON) 101 and two gate drivers (gate driver 102a and gate driver) 102b), where the timing controller 101 can output the STV signal (frame start signal), OE signal (output enable signal), and CPV signal (clock signal) for controlling the control of the gate driver 102a and the gate driver 102b signal. [0003] From figure 1 It can be seen that in the prior art, the signal transmission lines (103a, 103b, 103c, 103d) used to transmit STV signals, OE signals, and CPV signals all start from the timing controller 101 and enter the glass panel of the array substrate. Then it enters the gate driver 102a close to the timing contr...

Claims

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Application Information

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IPC IPC(8): G09G3/32G09G3/36G02F1/133G09G3/3208
Inventor 许益祯李卫海孙志华汪建明张亮
Owner BOE TECH GRP CO LTD