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CDR (Clock Data Recovery) circuit and terminal

A circuit and terminal technology, applied in the field of network communication, can solve the problems of difficult clock synchronization of CDR circuits, etc.

Active Publication Date: 2014-12-03
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides a CDR circuit and a terminal to solve the problem in the prior art that it is difficult for the CDR circuit in the terminal to complete clock synchronization with the peer terminal within a preset time

Method used

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  • CDR (Clock Data Recovery) circuit and terminal
  • CDR (Clock Data Recovery) circuit and terminal
  • CDR (Clock Data Recovery) circuit and terminal

Examples

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Embodiment Construction

[0022] The following embodiments of the present invention provide a CDR circuit and a terminal, so as to realize the EEE function of the terminal.

[0023] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, and to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, the following describes the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings For further detailed explanation.

[0024] The embodiment of the present invention is applied in EEE, and the EEE standard is used for dynamic energy saving according to the characteristics of network traffic. see figure 1 , which is a schematic diagram of the working state in the terminal implementing the EEE function in the embodiment of the present invention:

[0025] figure 1 In the ACTIVE mode of normal opera...

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PUM

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Abstract

Embodiments of the present invention disclose a CDR circuit and a terminal, where the CDR circuit is configured to perform clock synchronization in a terminal with EEE function, and the CDR circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a REFRESH state from a QUIET state, the CDR circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the CDR.

Description

technical field [0001] The present invention relates to the technical field of network communication, in particular to a CDR (Clock Data Recovery, clock data recovery) circuit and a terminal. Background technique [0002] When accessing the network through terminal devices such as PCs (Personal Computers, personal computers) and ordinary servers, for example, browsing the web, the network traffic generally increases sharply at the moment of clicking the URL, and the traffic decreases after the web page is loaded. During the browsing process, basically Network traffic is not required, and in view of the pulse-like change characteristics of network traffic, an EEE (Energy Efficient Ethernet, Energy Efficient Ethernet) standard is proposed in the prior art to dynamically save energy according to the characteristics of network traffic. Network traffic is usually based on Internet-level transmission, in which the PHY layer converts physical signals. When the MAC (Media Access Con...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L7/033
CPCH04L7/0083H04L7/02H03L7/00
Inventor 张雪坤张金弟俞波尹法纪
Owner HUAWEI TECH CO LTD
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