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Method and apparatus for timed shutdown

A related and circuit technology, applied in delay line applications, special data processing applications, instruments, etc., can solve problems such as prolonging the design cycle, failing to meet speed and power targets, etc.

Inactive Publication Date: 2016-04-06
MARVELL WORLD TRADE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore prolonging the design cycle and often missing original speed and power targets when timing is turned off

Method used

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  • Method and apparatus for timed shutdown
  • Method and apparatus for timed shutdown
  • Method and apparatus for timed shutdown

Examples

Experimental program
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Embodiment Construction

[0021] figure 1 A block diagram of an integrated circuit 100 according to one embodiment of the disclosure is shown. Note that integrated circuit 100 may be an integrated circuit (IC) chip, an IC package, or a circuit block, such as an intellectual property (IP) block within an IC chip. Integrated circuit 100 includes at least one pair of competing paths, such as path 120 and path 140 . In general, timing margins (such as setup time margins, hold time margins, etc.) are used to indicate how "worst-case" the timing of competing paths can be without causing circuit failures, and a positive timing margin. In one example, a negative setup time margin indicates that the timing of competing paths does not have sufficient margin and may cause circuit failure in the worst case of setup time; Executes the correct function in the worst case. A positive setup time margin allows for unexpected situations and is desirable to ensure correct circuit function under unexpected circumstance...

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PUM

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Abstract

Some aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have a substantial match of the first circuit in response to at least one parameter change of manufacturing, environmental and operating parameters such as process variations, temperature variations, and supply voltage variations delay characteristics.

Description

technical field [0001] This application claims the No. 61 / 384,058 U.S. provisional application "Delay Compensation Apparatus and Method for Multi-Corner Multi-Mode (MCMM) Timing Closure " submitted on September 17, 2010 and No. 61 / 432,557 U.S. provisional application submitted on January 13, 2011 Interest in "Delay Compensation Apparatus and Method for Multi-Corner Multi-Mode (MCMM) Timing Closure", these two US provisional applications are hereby incorporated by reference in their entirety. Background technique [0002] The background description provided herein is for the purpose of generally presenting the context of the disclosure. The work of the presently named inventor is neither expressly nor impliedly admitted to the extent that this work is described in this Background Section and aspects of that description that would not otherwise be qualified as prior art at the time of filing. Prior Art of the Disclosure. [0003] In general, multi-knee and multi-mode (MCMM) ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCH03K5/159H03K2005/00013G06F30/3312G06F30/30G06F2119/12G01R31/31725
Inventor J·T·苏W·李
Owner MARVELL WORLD TRADE LTD