Method and apparatus for timed shutdown
A related and circuit technology, applied in delay line applications, special data processing applications, instruments, etc., can solve problems such as prolonging the design cycle, failing to meet speed and power targets, etc.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0021] figure 1 A block diagram of an integrated circuit 100 according to one embodiment of the disclosure is shown. Note that integrated circuit 100 may be an integrated circuit (IC) chip, an IC package, or a circuit block, such as an intellectual property (IP) block within an IC chip. Integrated circuit 100 includes at least one pair of competing paths, such as path 120 and path 140 . In general, timing margins (such as setup time margins, hold time margins, etc.) are used to indicate how "worst-case" the timing of competing paths can be without causing circuit failures, and a positive timing margin. In one example, a negative setup time margin indicates that the timing of competing paths does not have sufficient margin and may cause circuit failure in the worst case of setup time; Executes the correct function in the worst case. A positive setup time margin allows for unexpected situations and is desirable to ensure correct circuit function under unexpected circumstance...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 