finfet with metal gate stressor

Abstract

Provides gate stressors for fin field effect transistor (FinFET) devices. The gate stressor includes a bottom surface, a first stressor sidewall, and a second stressor sidewall. A bottom surface is formed on the first portion of the gate layer. A gate layer is disposed on shallow trench isolation (STI) regions. A first stressor sidewall is formed on the second portion of the gate layer. A second portion of the gate layer is disposed on the sidewalls of the fin. A second stressor sidewall is formed on the third portion of the gate layer. A third portion of the gate layer is disposed on a sidewall of the structure spaced from the fin. The first stressor sidewall and the second stressor sidewall do not exceed the height of the fin.

Description

technical field [0001] The present invention relates generally to the field of semiconductor technology, and more particularly to field effect transistors. Background technique [0002] Semiconductor devices are used in a large number of electronic devices such as computers, cell phones, and the like. Semiconductor devices, including integrated circuits, are formed on semiconductor wafers by depositing various types of thin film materials on the semiconductor wafers, and patterning the thin film materials to form the integrated circuits. Integrated circuits include field effect transistors (FETs), such as metal oxide semiconductor (MOS) transistors. [0003] One of the goals of the semiconductor industry is to continue to shrink the size and increase the speed of individual FETs. To achieve these goals, fin FETs (FinFETs) or multi-gate transistors are used in transistor nodes below 32nm. For example, FinFETs not only increase the area density, but also improve the gate co...

AI Technical Summary

Problems solved by technology

[0005] Known replacement gate process also poses limitations that attract more attention as technology advances, integration levels increase, and feature sizes shrink

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