A Wafer Acceptance Test Structure

Abstract

The invention discloses a wafer accept test structure. The wafer accept test structure combines two sets of test patterns, not only can monitor the problem of failures of metal interconnection layers, but also can monitor the problem of failures of connecting holes between the metal interconnection layers. Thus, the wafer accept test structure can more effectively and comprehensively monitor the problem of failures of MOM devices.

Description

technical field [0001] The present application relates to the field of integrated circuit manufacturing, in particular to a Wafer Acceptance Test (WAT, Wafer Acceptance Test) structure. Background technique [0002] With the advancement of technology, the requirements of the integrated circuit manufacturing process are increasing day by day, and because the integrated circuit manufacturing cycle is long and the cost is high, it is particularly important to improve the manufacturing efficiency and quality of the manufacturing process. [0003] In the integrated circuit manufacturing process, the industry usually manufactures WAT structures in the dicing lanes around each integrated circuit chip of the wafer, and then detects the WAT structures after the manufacturing is completed to test the corresponding manufacturing process. If the WAT structure is found to have failures such as short circuit, open circuit or leakage when performing various tests such as electrical testing...

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Problems solved by technology

However, it should be noted that in fact there are connection holes between the metal interconnection layers, and there is capacitance between the connection holes of the same metal interconnection layer, but the WAT structure of the prior art cannot obtain the connection holes of the same metal interconnection layer The capacitance value between, that is to say, the WAT structure of the prior art cannot test the capacitance failure caused by the abnormality of the connection hole

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