Management method and device of cache

A management method, a technology of physical addresses, applied in the field of Cache (cache) management

Active Publication Date: 2015-07-29
HUAWEI TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Embodiments of the present invention provide a Cache management method and device, which can solve the problem of how to improve the utilization rate of cache resources

Method used

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  • Management method and device of cache
  • Management method and device of cache
  • Management method and device of cache

Examples

Experimental program
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Embodiment 1

[0078] This embodiment provides a cache management method. In this embodiment, a plurality of cache subunits are set in the cache, and each cache subunit includes a plurality of cache lines; wherein, the length of the cache line included in each cache subunit is the same as that of other cache subunits The included cache line lengths are different from each other; each of the cache subunits is used to store data of a corresponding level, and the level is the spatial locality level of the data, wherein the cache subunit is the same as the level The corresponding relationship is: the cache line length included in the cache subunit is positively correlated with the spatial locality strength of the data.

[0079] For ease of understanding, this embodiment provides a schematic diagram of an organization manner of different cache line lengths in a cache for reference. Such as figure 2 As shown, the cache subunit 201, the cache subunit 202, and the cache subunit 203 constitute the...

Embodiment 2

[0092] exist image 3 On the basis of the illustrated embodiments, the embodiments of the present invention further provide a cache management method. Such as Figure 4 As shown, the method provided in this embodiment includes:

[0093] 401. Set multiple cache subunits in the cache; wherein, each cache subunit includes multiple cache lines, and the length of the cache lines included in each cache subunit is different from the lengths of the cache lines included in other cache subunits. same.

[0094] Specifically, the cache can be divided by way, the multiple cache subunits are determined, and the cache line length of each cache subunit is set;

[0095] And / or, divide the cache according to group set, determine the multiple cache subunits, and set the cache line length of each cache subunit.

[0096] 402. The cache receives the access request, and determines the data to be accessed that needs to be accessed by the access request.

[0097] It is worth noting that the metho...

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Abstract

The present invention relates to the field of communications. Disclosed are a cache management method and device for solving the problem of how to improve cache resource utilization. The method comprises: receiving an access request and determining data to be accessed by the access request (301); judging the strength level of the spatial locality of the data to be accessed (302); and according to the strength level of the spatial locality of the data to be accessed, allocating a cache subunit corresponding to the level for the data to be accessed (303). The present invention is used for cache management in the field of communications.

Description

technical field [0001] The present invention relates to the communication field, in particular to a Cache (cache memory) management method and device. Background technique [0002] During the development of computer technology, the access speed of the main memory has always been much slower than the processing speed of the CPU (processor), so that the high-speed processing capability of the CPU cannot be fully utilized, and the work efficiency of the entire computer system is affected. In order to alleviate the contradiction between the speed mismatch between the CPU and the main memory, a more commonly used method is to use a cache (high-speed cache) for caching at the storage level. For example, the cache can be integrated in the CPU so that the CPU can obtain data faster. figure 1 A schematic structural diagram of an N-way (way) set associative Cache is provided. Such as figure 1 As shown, the size of all cache lines (Cacheline) in the cache is the same, and each cache...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F12/0811G06F12/0848G06F12/0864G06F2212/1024G06F2212/601G06F12/0862G06F12/0886G06F12/0895G06F2212/1044G06F2212/603G06F11/3037G06F11/3452G06F2201/885G06F12/023G06F2212/1041G06F2212/281G06F2212/282G06F2212/6042G06F2212/608
Inventor 黄永兵陈明宇张坤
Owner HUAWEI TECH CO LTD
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