Device and method for floating point complex number parallel addition and subtraction
A technology of floating-point complex numbers and floating-point numbers, which is applied in the direction of electrical digital data processing, digital data processing components, instruments, etc., can solve the problems of reducing computing efficiency and not giving full play to the superiority of vector computing, and achieve the effect of avoiding poor efficiency
Active Publication Date: 2015-08-26
北京国睿中数科技股份有限公司
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Problems solved by technology
For example, in digital signal processing, some common operations (such as integral operations) are performed on time-continuous data. If the traditional vector operation method is used, frequent shift alignment operations are required, which cannot give full play to the advantages of vector operations. superiority, and even lead to reduced computing efficiency
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[0028] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. On the contrary, the embodiments of the present invention include all changes, modifications and equivalents coming within the spirit and scope of the appended claims.
[0029] In the description of the present invention, it should be understood that the terms "first", "second" and so on are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance. In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "connected" and "connect...
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The invention discloses a device and method for floating point complex number parallel addition and subtraction. The device comprises a plurality of source vector registers, a data selector, an arithmetic unit and a target vector register, wherein each source vector register is used for storing a plurality of floating point complex numbers; each floating point complex number comprises a floating point number serving as a real part and a floating point number serving as a virtual part; the data selector is used for reading the real part floating point numbers and the virtual part floating point numbers of the floating point complex numbers in each source vector register, and pairwise transmitting the real part floating point numbers and the virtual part floating point numbers in each source vector register to the arithmetic unit respectively; the arithmetic unit is used for performing operation on data read by the data selector according to an operation type and a data type; and the target vector register is used for storing the operation result of the arithmetic unit. According to the device, parallel addition and subtraction operation of the floating point complex numbers is realized through different data provided for the arithmetic unit by the data selector, so that hardware resources are saved.
Description
technical field [0001] The invention relates to the technical field of microprocessor architecture, in particular to a device and method for parallel addition and subtraction of floating-point complex numbers. Background technique [0002] With the rapid development of digital communication technology, the requirements for digital signal processing capabilities are getting higher and higher. Vector operations can greatly accelerate the processing of digital signals by using the parallelism of hardware, and are increasingly used in the field of digital communication. . [0003] At present, the signal processing technology widely used in communication is OFDM technology, which can reduce the mutual interference between channels by dividing the channel into several orthogonal sub-channels, and can allow each sub-carrier to have Partially overlapping, thereby improving bandwidth utilization. Because complex numbers can contain mutually irrelevant real and imaginary parts, they...
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IPC IPC(8): G06F7/485H04L27/26
Inventor 李祖松杨思博樊广超何苗平
Owner 北京国睿中数科技股份有限公司