Apparatus and method for parallel addition and subtraction of floating-point complex numbers
A floating-point complex number, floating-point number technology, applied in electrical digital data processing, digital data processing components, instruments, etc., can solve the problems of reducing operation efficiency, unable to give full play to the advantages of vector operations, etc., to avoid the effect of poor efficiency
Active Publication Date: 2018-05-18
北京国睿中数科技股份有限公司
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Problems solved by technology
For example, in digital signal processing, some common operations (such as integral operations) are performed on time-continuous data. If the traditional vector operation method is used, frequent shift alignment operations are required, which cannot give full play to the advantages of vector operations. superiority, and even lead to reduced computing efficiency
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[0028] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. On the contrary, the embodiments of the present invention include all changes, modifications and equivalents coming within the spirit and scope of the appended claims.
[0029] In the description of the present invention, it should be understood that the terms "first", "second" and so on are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance. In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "connected" and "connect...
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The invention discloses a device and method for parallel addition and subtraction of floating-point complex numbers, wherein the device includes: a source vector register, a data selector, an operator, and a target vector register, wherein there are multiple source vector registers, each The source vector register is used to store multiple floating-point complex numbers, each floating-point complex number contains a floating-point number as the real part and a floating-point number as the imaginary part; the data selector is used to read the floating-point number in each source vector register The floating-point number of the real part and the floating-point number of the imaginary part of the complex number, and send the floating-point number of the real part and the floating-point number of the imaginary part in pairs of each source vector register to the operator; the operator is used for Operate the data read by the data selector according to the operation type and data type; the target vector register is used to save the operation result of the arithmetic unit. The device of the invention realizes the parallel addition and subtraction of floating-point complex numbers by providing different data to the arithmetic unit through the data selector, thereby saving hardware resources.
Description
technical field [0001] The invention relates to the technical field of microprocessor architecture, in particular to a device and method for parallel addition and subtraction of floating-point complex numbers. Background technique [0002] With the rapid development of digital communication technology, the requirements for digital signal processing capabilities are getting higher and higher. Vector operations can greatly accelerate the processing of digital signals by using the parallelism of hardware, and are increasingly used in the field of digital communication. . [0003] At present, the signal processing technology widely used in communication is OFDM technology, which can reduce the mutual interference between channels by dividing the channel into several orthogonal sub-channels, and can allow each sub-carrier to have Partially overlapping, thereby improving bandwidth utilization. Because complex numbers can contain mutually irrelevant real and imaginary parts, they...
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IPC IPC(8): G06F7/485H04L27/26
Inventor 李祖松杨思博樊广超何苗平
Owner 北京国睿中数科技股份有限公司