FPGA realization module and FPGA realization method for signal subspace decomposition by time-sharing multiplexing of hardware resources

A technology of signal subspace and hardware resources, applied in the field of FPGA implementation modules, can solve the problems of consuming hardware resources and reducing the speed of decomposition

Inactive Publication Date: 2016-05-25
HEFEI UNIV OF TECH
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Problems solved by technology

However, the estimation and calculation of the number of signal sources based on the AIC criterion based on information theory involves a large number of logarithmic operations, which requires a coprocessor for logarithmic operations in the hardware system. Therefore, the realization of FPG

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  • FPGA realization module and FPGA realization method for signal subspace decomposition by time-sharing multiplexing of hardware resources
  • FPGA realization module and FPGA realization method for signal subspace decomposition by time-sharing multiplexing of hardware resources
  • FPGA realization module and FPGA realization method for signal subspace decomposition by time-sharing multiplexing of hardware resources

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Embodiment Construction

[0062] In this embodiment, an FPGA implementation module for signal subspace decomposition of time-division multiplexing hardware resources, including an automatic sorting pass Jacobi algorithm unit and a space signal source number estimation calculation unit;

[0063] In this embodiment, the overall execution flow chart of the Jacobi algorithm for automatic sorting is as follows: figure 1 As shown, the automatically sorted clearance Jacobi unit reads the N-order covariance matrix Α=[a pq ] n×n And perform operations to obtain a diagonal matrix Α of order N k ;diagonal matrix Α k The elements on the main diagonal of are the eigenvalues ​​λ of the Nth order covariance matrix A 1 ,λ 2 ,...,λ p ,...,λ q ,...,λ n ; and λ 1 ,λ 2 ,...,λ p ,...,λ q ,...,λ n Sort in descending order; 1≤p≤n; 1≤q≤n; p≠q;

[0064] In the specific implementation, if the number of array elements is set to be 8, then the covariance matrix Α is an 8-order matrix, 64 elements are arranged in Α, a...

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Abstract

The invention discloses an FPGA realization module and an FPGA realization method for signal subspace decomposition by time-sharing multiplexing of hardware resources. The module is characterized by comprising an automatic sorting type pass Jacobi algorithm unit and a spatial signal source number estimation calculation unit, wherein the automatic sorting type pass Jacobi algorithm unit is used for obtaining an N-order diagonal matrix; and the spatial signal source number estimation calculation unit is used for obtaining a number estimation value of a signal source. According to the FPGA realization module and the FPGA realization method, the same group of hardware structures in an FPGA can be subjected to time-sharing multiplexing on the premise of meeting the speed requirement, so that the hardware resources are saved and the flexibility is improved; and therefore, accurate and quick calculation of signal subspace decomposition in a MUSIC algorithm is realized.

Description

technical field [0001] The invention belongs to the technical field of array signal processing, and specifically relates to an FPGA realization module and an FPGA realization method of signal subspace decomposition of time-division multiplexing hardware resources. Background technique [0002] Since the end of the 1970s, a large number of research results and literatures have emerged in the area of ​​spatial spectrum estimation. Direction of Arrival (DOA) estimation is an important topic in the study of spatial spectrum estimation. For the same reference signal source, there is a phase difference between the signals received by each antenna element, thus forming harmonics. Signal sources in different directions correspond to different harmonic frequencies. As long as each harmonic frequency is estimated, Then the direction of arrival of each corresponding signal source can be obtained. The initial DOA estimation method is a linear spectrum estimation method based on Fourier...

Claims

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Application Information

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IPC IPC(8): G06F17/16
CPCG06F17/16
Inventor 张多利李怡洵宋宇鲲
Owner HEFEI UNIV OF TECH
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