Pixel internal memory unit, pixel internal data storage method and pixel array

Abstract

The invention discloses a pixel internal memory unit, a data storage method, and a pixel array. The pixel internal memory unit includes a data input circuit, a first data latch circuit, a second data latch circuit, a driving control circuit and a driving circuit. The data input circuit enables a digital voltage of a data line to be applied over a first data latch end and a second data latch end when a first control signal of a first control signal end is at an active level. The first data latch circuit is configured to maintain the level of the first data latch end. The second data latch circuit is configured to maintain the level of the second data latch end. The driving control circuit is configured to enable the level of a driving node to be opposite to the level of the first data latch end. The driving circuit is configured to output a third power voltage of a third power voltage end to an output end when the driving node is at an active level thereof, and outputs a fourth power voltage of a fourth power voltage end to the output end when the second data latch end is at an active level thereof.

Description

technical field [0001] The present invention relates to storage of data voltage in a pixel, and more particularly to a storage unit in a pixel, a method for storing data in a pixel, and a pixel array. Background technique [0002] At present, with the development of technologies such as smart wear and mobile applications, higher requirements are put forward for the development of ultra-low power consumption liquid crystal LCD display technology. Memory in Pixel (MIP) display technology, as a new type of low-power LCD display technology, has broad development prospects due to its characteristics of no need to change the LCD process, no need to develop new materials, simple structure, and low cost. [0003] However, the current MIP display technology is basically a CMOS LTPS process, and the memory cells in the pixels in the MIP display technology are all composed of CMOS circuits. This process is complex and has a low yield rate, which greatly increases the cost of MIP displa...

Images