Method and system for debugging operating state of CPU under multiple CPU frameworks

Abstract

The invention provides a method and system for debugging an operating state of a CPU under multiple CPU frameworks. The method for debugging the operational state of the CPU comprises the steps of starting a first CPU through a debugging interface, and arranging a debugging result shared address in a public storage through the first CPU; controlling the first CPU to write a second CPU jump instruction into a second CPU jump instruction storing address of the public storage through the debugging interface; controlling the first CPU to write an operating debugging instruction into the debugging instruction storing address through the debugging interface; controlling the second CPU to read the operational debugging instruction from the debugging instruction storing address according to the second CPU jump instruction, debugging the operational state of the second CPU, and writing a debugging result of the operational state into a debugging result shared address; controlling the first CPU to read the debugging result of the operational state from the debugging result shared address through the debugging interface. According to the technical scheme, debugging can be conducted on the operational state of the CPU which does not have the debugging interface.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, and more specifically, to a method and system for debugging CPU running states under a multi-CPU architecture. Background technique [0002] SOC chip (System-on-a-Chip, system-on-a-chip) is the chip integration at the core of the information system, which can integrate the key components of the system on one chip. Usually, the SOC chip includes multiple CPUs (Central Processing Unit, central processing unit), and its architecture mode is a multi-CPU architecture. [0003] With the development of information technology, the tasks of SOC chips are becoming more and more complex, the calculation speed is getting faster and the response time is getting shorter and shorter, resulting in higher and higher integration of SOC chips. The improvement of the integration level of the SOC chip will lead to a larger and larger chip area, an increasing number of pins and an increasing cost....

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a technical solution for CPU running state debugging under a multi-CPU architecture, to solve the problem that the CPU in the SOC chip whose debugging interface is partly cut off in the prior art described in the background technology is difficult to be normally debugged

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