A CPU running state debugging method and system under a multi-CPU architecture
A technology of running state and debugging method, which is applied in the direction of fault hardware test method, detection of faulty computer hardware and instruments, etc., can solve the problem that the CPU is difficult to be debugged normally.
Active Publication Date: 2020-04-07
HUNAN GOKE MICROELECTRONICS
View PDF7 Cites 0 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
[0005] The purpose of the present invention is to provide a technical solution for CPU running state debugging under a multi-CPU architecture, to solve the problem that the CPU in the SOC chip whose debugging interface is partly cut off in the prior art described in the background technology is difficult to be normally debugged
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0067] The CPU running state debugging solution under the multi-CPU architecture provided by the embodiment of the present invention solves the problem that some CPUs in the SOC chip with the debugging interface cut off are difficult to be normally debugged under the multi-CPU architecture introduced in the background art.
[0068] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, and to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention are described below in conjunction with the accompanying drawings The program is described in further detail.
[0069] Please refer to the attached figure 1 , figure 1 It is a schematic diagram of an application scenario shown in an exemplary embodiment of the present invention. like figure 1 As shown, the a...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention provides a method and system for debugging an operating state of a CPU under multiple CPU frameworks. The method for debugging the operational state of the CPU comprises the steps of starting a first CPU through a debugging interface, and arranging a debugging result shared address in a public storage through the first CPU; controlling the first CPU to write a second CPU jump instruction into a second CPU jump instruction storing address of the public storage through the debugging interface; controlling the first CPU to write an operating debugging instruction into the debugging instruction storing address through the debugging interface; controlling the second CPU to read the operational debugging instruction from the debugging instruction storing address according to the second CPU jump instruction, debugging the operational state of the second CPU, and writing a debugging result of the operational state into a debugging result shared address; controlling the first CPU to read the debugging result of the operational state from the debugging result shared address through the debugging interface. According to the technical scheme, debugging can be conducted on the operational state of the CPU which does not have the debugging interface.
Description
technical field [0001] The present invention relates to the technical field of integrated circuits, and more specifically, to a method and system for debugging CPU running states under a multi-CPU architecture. Background technique [0002] SOC chip (System-on-a-Chip, system-on-a-chip) is the chip integration at the core of the information system, which can integrate the key components of the system on one chip. Usually, the SOC chip includes multiple CPUs (Central Processing Unit, central processing unit), and its architecture mode is a multi-CPU architecture. [0003] With the development of information technology, the tasks of SOC chips are becoming more and more complex, the calculation speed is getting faster and the response time is getting shorter and shorter, resulting in higher and higher integration of SOC chips. The improvement of the integration level of the SOC chip will lead to a larger and larger chip area, an increasing number of pins and an increasing cost....
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22
CPCG06F11/2242G06F11/2273
Inventor 杨艳刘杰兵朱健余方桃黄新军
Owner HUNAN GOKE MICROELECTRONICS