Method with compatibility with I2C communication and IPMB communication

Abstract

The invention provides a method with compatibility with I2C communication and IPMB communication. When performing communication with I2C slave equipment, standard I2C data reading-writing operation is performed, and delivery of a read command and a write command is performed according to needs. An I2C clock is generated under the control of a BMC, a data line is pulled down to generate an initial signal, an address and data are transmitted according to a protocol, and after transmission is completed, a stop signal is sent out to complete the transmission of the command; when communicating with ME, data writing is still subjected to a normal I2C register writing process according to an IPMB protocol, and when the operation of reading data is performed, ME sends a start signal to the BMC, and generates a clock and a write request. The method has the advantages as follows: rapid switching of the I2C master-slave mode is achieved, meanwhile compactness of a data link is ensured without occupying the additional link, the module completely has complete compatibility with normal I2C communication and IPMB communication, and thus a resource utilization rate is greatly improved.

Description

technical field [0001] The invention relates to a serial bus communication method. Background technique [0002] The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS for connecting microcontrollers and their peripherals. It is a bus standard widely used in the field of microelectronics communication control. It is a special form of synchronous communication, which has the advantages of less interface lines, simple control mode, small device package, and high communication rate. [0003] I2C communicates information between devices connected to the bus through the Serial Data (SDA) and Serial Clock (SCL) lines. Each device has a unique address identification, and can be used as a transmitter or receiver (determined by the function of the device). The master is the device that initiates the data transfer on the bus and generates the clock signals that allow the transfer. At this point, any addressed device is considered a slave. [0004] IP...

AI Technical Summary

Problems solved by technology

[0022] 5. The I2C notification mechanism (ACK bit) only indicates that the byte is received by the slave, and cannot guarantee the integrity and correctness of the received data

This technology uses an additional expansion chip to achieve IPMB compatibility, which not only occupies circuit board resources, but may also generate additional delays and affect communication performance

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