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Power Delivery Network (PDN) Design for Monolithic Three-Dimensional (3-D) Integrated Circuits (ICs)

A technology of integrated circuits and power transmission, which is applied in the direction of circuits, electrical components, and electrical solid-state devices

Active Publication Date: 2019-11-19
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, monolithic 3D-ICs face challenges when it comes to power delivery

Method used

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  • Power Delivery Network (PDN) Design for Monolithic Three-Dimensional (3-D) Integrated Circuits (ICs)
  • Power Delivery Network (PDN) Design for Monolithic Three-Dimensional (3-D) Integrated Circuits (ICs)
  • Power Delivery Network (PDN) Design for Monolithic Three-Dimensional (3-D) Integrated Circuits (ICs)

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Embodiment Construction

[0019] Aspects of the invention are disclosed in the following description and related drawings directed to specific aspects of the invention. Alternative aspects can be designed without departing from the scope of the invention. In addition, well-known elements of the present invention will not be described in detail or omitted so as not to obscure relevant details of the present invention.

[0020] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily understood to be preferred or advantageous over other aspects. Likewise, the term "aspects of the invention" does not require that all aspects of the invention include the discussed feature, advantage or mode of operation.

[0021] The terms used herein are only for the purpose of describing specific aspects and are not intended to limit aspects of the present invention. As used herein, the singular forms "a / an" and "the" are i...

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Abstract

Systems and methods relate to a power delivery network PDN for a monolithic three-dimensional integrated circuit 3D-IC. A monolithic 3D-IC (400) includes a first die (404) adjacent to and in contact with power / ground bumps (402). A second die (406) is stacked on the first die (404), the second die being separated from the power / ground bumps by the first die. One or more bypass power / ground vias (432) and one or more monolithic interlayer vias MIV (430) configured to deliver power from the power / ground bumps (402) to the first Two Die (406).

Description

Technical field [0001] The disclosed aspect relates to a power delivery network (PDN) for monolithic three-dimensional integrated circuits (3D-IC). More precisely, the exemplary aspect relates to the use of a bypass power / ground (P / G) via array and a P / G monolithic interlayer via (MIV) array in a monolithic 3D-IC to support vertical power delivery. Background technique [0002] Three-dimensional integrated circuits (3D-IC) have emerged as a promising solution to extend the 2D zoom trajectory predicted by Moore's Law. Currently, through-silicon vias (TSV) are used to form 3D-ICs to allow vertical stacking of multiple dies manufactured separately. However, the quality of TSV-based 3D-ICs largely depends on the size of TSVs and parasitic elements, and is limited to memory-mounted logic or large-scale logic-mounted logic designs with a relatively small amount of global interconnection. [0003] An emerging alternative to TSV-based 3D-IC is monolithic 3D-IC (also known as "M3D"). Mon...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/065H01L23/48H01L23/528
CPCH01L23/5286H01L27/0688H01L2224/131H01L2224/32145H01L2224/73153H01L2225/06527H01L2225/06513H01L2225/06565H01L2225/06544H01L23/481H01L25/0657H01L2924/10253H01L2924/014H01L2924/00014H01L24/05H01L24/11H01L24/14H01L25/50H01L2224/05147H01L2225/06541
Inventor 李圣奎卡姆比兹·萨玛迪杜杨
Owner QUALCOMM INC