A method and apparatus for increasing NandFlash bus timing margin

Abstract

The invention discloses a method for increasing NandFlash bus timing margin, a DEVICE, an APPARATUS, AND a COMPUTER READABLE STORAGE MEDIUM. The method comprises the following steps: acquiring the current voltage value, the voltage value before charging, the voltage value after charging, the bus equivalent resistance value and the setting charging time value of the designated point on the NandFlash bus; setting the charging time value as the time required for the voltage value of the designated point to change from the voltage value before charging to the voltage value after charging; calculating a bus equivalent capacitance value of the NandFlash bus based on a current voltage value, a voltage value before charging, a voltage value after charging, a bus equivalent resistance value and a set charging time value; based on the bus equivalent capacitance value and the load capacitance value of the NandFlash bus, the capacitance value of the specific capacitance to be increased being calculated, and the specific capacitance being serially connected with the load capacitance corresponding to the load capacitance value. The present application is capable of increasing the timing margin of the bus and increasing the operating speed.

Description

technical field [0001] The present invention relates to the technical field of NandFlash bus, and more specifically, relates to a method, device, equipment and computer-readable storage medium for improving the timing margin of NandFlash bus. Background technique [0002] The NandFlash bus is a parallel storage bus that adopts a non-linear macrocell mode inside; with the advent of the era of big data, there is an increasing demand for "increasing the storage capacity per unit volume of a product" and "reducing the delay of the entire system". Strongly, "large capacity" means that the number of dies mounted on a single channel on the NandFlash bus will gradually increase, and the load capacitance will become larger and larger; "low latency" means that the operating speed requirements of the NandFlash bus will also become higher and higher. However, the larger the load capacitance, the more serious the edge degradation of the running signal, the smaller the timing margin windo...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a method, device, equipment and computer-readable storage medium for improving the timing margin of the NandFlash bus, which can solve the problems in the prior art that the timing margin of the NandFlash bus is relatively small due to the large load capacitance, Problem with slow running speed

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