A high-speed data encryption nvme-sata converter circuit

A converter circuit, high-speed data technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of low transmission rate, complex control process, high resource consumption, etc., and achieve the effect of achieving safety and reliability

Active Publication Date: 2022-02-15
BEIJING INST OF COMP TECH & APPL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, it is not a good solution to directly add an encryption unit to encrypt the transmitted data during the transmission of the NVMe protocol
Use software to control data in NVMe protocol format to encrypt, not only the control process is complicated, but also the resource consumption is high and the transmission rate is low

Method used

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  • A high-speed data encryption nvme-sata converter circuit
  • A high-speed data encryption nvme-sata converter circuit
  • A high-speed data encryption nvme-sata converter circuit

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Embodiment Construction

[0018] In order to make the purpose, content, and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0019] figure 1 Shown is a schematic diagram of a high-speed data encryption NVMe-SATA converter circuit of the present invention, figure 2 Shown is the schematic diagram of the encrypted computing array unit, such as figure 1 as well as figure 2 As shown, a high-speed data encryption NVMe-SATA converter circuit of the present invention includes: a high-speed data encryption NVMe bridge controller device 7, including: NVMe controller 1, system master controller 2, on-chip cache 3, SATA A controller 6, an encryption and decryption engine 9, and a key injection unit 10. The encryption and decryption engine 9 includes: an encryption and decryption engine controller 4 , an encryption and decryption calculation unit 5 ...

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PUM

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Abstract

The invention discloses a high-speed data encryption NVMe-SATA converter circuit, wherein, the host computer performs initial configuration through the NVMe controller, and the key injection unit injects the initial key into the system general controller to distribute the key, and the NVMe controllers respectively Send the received commands and data to the on-chip cache and SATA controller through the system master controller, and the encryption and decryption engine controller transfers the data from the on-chip cache to the cache register according to the command parameters configured by the system master controller. And read data from the cache register, write it into the on-chip cache, the cache register organizes the data into the corresponding data format and writes it to the encryption and decryption calculation unit for encryption and decryption processing, and writes the result back to the cache register. The SATA controller writes to the solid state disk or outputs the decrypted data through the NVMe controller; the system bus controller queries the status enable signal of the encryption and decryption engine, obtains the status of each encryption and decryption engine, and calls the idle encryption and decryption engine Perform encryption and decryption operations.

Description

technical field [0001] The invention relates to a high-speed data encryption NVMe-SATA converter circuit, in particular to a high-speed data encryption NVMe-SATA converter circuit chip architecture. Background technique [0002] In the era of traditional mechanical hard disks, the host uses the SATA transfer protocol and the AHCI user protocol to read and write to the hard disk. In the era of solid-state drives, the transfer rate of the SATA transfer protocol and the number and depth of queues supported by the AHCI user protocol can no longer meet actual needs. To solve this problem, a non-volatile memory host controller interface protocol (Non-Volatile Memory express) emerged as the times require, which solves the storage performance problem of the non-volatile memory. [0003] The NVMe protocol makes full use of the low-latency and parallelism characteristics of the PCIe transmission protocol channel, supports a huge number of queues and queue depths, greatly improves the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16G06F13/42
CPCG06F13/1668G06F13/42
Inventor 曲哲万星徐川杨博许静雯董其金郭慧波邓威罗崇安东博
Owner BEIJING INST OF COMP TECH & APPL
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