Hardware encryption and decryption system and method

Abstract

The invention provides a hardware encryption and decryption system and method. The hardware encryption and decryption system comprises a receiving buffer module, an allocation module, an algorithm pool, a collection module, an intermediate buffer module and a sending buffer module which are integrated in an encryption and decryption chip. The hardware encryption and decryption system and method can call algorithms in an algorithm pool for data packets which are sent into the encryption and decryption chip and have different protocols for multiple times; the encryption and decryption of the data packet is completed through the encryption and decryption processing module and the output of the data packet which is completely processed at the sending buffer module, the whole encryption and decryption processing process does not need logic processing of a processor, the operation load of the processor is reduced, maximum utilization of algorithm resources is realized, and the encryption anddecryption processing efficiency of the data packet is effectively improved.

Description

technical field [0001] The invention relates to the technical field of data security, in particular to a hardware encryption and decryption system and method. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. [0003] In the information age where information security is increasingly valued by people, data processing and storage products require not only the function of processing data, but also the functions of virus protection and encryption and decryption. In response to this requirement, there are currently two schemes on the market, software encryption and decry...

AI Technical Summary

Problems solved by technology

However, since the encryption and decryption process of a data packet may need to undergo multiple algorithm (such as SM3, SM4, etc.) processing, and after each algorithm processing is completed, it needs to be traced back to the CPU to re-plan the data packets that have not completed the encryption and decryption process. Once the algorithm is processed until the data packet completes all the encryption and decryption algorithm steps; however, in the above encryption and decryption process, the data packet needs to be sent back multiple times between the CPU and the FPGA to complete the encryption and decryption process, which increases the resource utilization of the CPU , increasing the operating load of the CPU; at the same time, the multiple return process will also reduce the efficiency of data packet encryption and decryption processing

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