A Magnetic Random Access Memory with Error Correction and Compression Circuit

Abstract

The invention provides a magnetic random access memory with an error correction and compression circuit, including a memory cell array, an error detection and correction circuit, a compression and decompression circuit, a control circuit, a status bit buffer, and a data buffer; the chip reads the operation steps as follows : The first compressed data is obtained in the memory cell array, the first compressed data is processed by an error detection and correction circuit, the processed first compressed data is decompressed by a compression and decompression circuit, and the first data is obtained and output; the chip writes The input operation steps are as follows: the second data to be written is compressed by the compression and decompression circuit to obtain the second compressed data, and the second compressed data is processed by the error detection and correction circuit and then written into the memory cell array.

Description

technical field [0001] The invention relates to a storage device, in particular to a magnetic random access memory with error correction and compression circuits, and belongs to the technical field of semiconductor chips. Background technique [0002] MRAM is a new memory and storage technology that can be read and written as fast as SRAM / DRAM, and can permanently retain data after power failure like Flash memory. Its economy is quite good, and the silicon area occupied per unit capacity has a great advantage over SRAM, and also has advantages over NOR Flash, which is often used in such chips, and has greater advantages than embedded NOR Flash. Its performance is also quite good, the read and write latency is close to the best SRAM, and the power consumption is the best among various memory and storage technologies. Moreover, unlike DRAM and Flash, MRAM is not compatible with standard CMOS semiconductor processes. MRAM can be integrated into a chip with logic circuits. [...

Images