A kind of synchronization circuit and synchronization method based on ddr read data integer clock cycle

Abstract

The invention discloses a synchronization circuit and a synchronization method based on an integer clock cycle of DDR read data. The synchronization circuit includes: a physical layer calibration circuit connected to each other and a read data effective enable generation circuit; the physical layer calibration circuit is used for DDR read data Delay multi-shot enable comparison with the reference data to obtain the comparison result; the read data effective enable generation circuit is used to determine the integer clock cycle for the DDR read data to reach the DDR physical layer according to the comparison result, and determine the effective enable delay of the DDR read data The integer clock cycle of the DDR read data integer clock cycle is synchronized. The present invention adopts the method of delaying multi-shot enabling comparison signals to determine the integer clock cycle for DDR read data to reach the DDR physical layer, effectively enabling the data to delay the corresponding integer clock cycle, and realizing DDR read data integer clock cycle synchronization.

Description

technical field [0001] The invention relates to the technical field of DDR, in particular to a synchronous circuit and a synchronous method based on an integer clock cycle of DDR read data. Background technique [0002] According to the DDR protocol, after the DDR controller issues a read command, after several DDR clock cycles, the DDR particles will return DQS and DQ, and the physical layer of the controller needs to process the received data (DQ) to the internal clock of the controller. On the domain, it is dfi_rddata on the physical layer interface, and the corresponding effective control is dfi_rddata_valid. Due to the uncertainty of the connection delay between the IO (input and output port) and the board level, it is difficult to determine the phase of the data received by the DDR physical layer and the internal clock. This phase includes the phase of the integer clock cycle and the fractional clock cycle. [0003] The processing method in the prior art is to calcula...

AI Technical Summary

Problems solved by technology

Due to the uncertainty of the connection delay between the IO (input and output port) and the board level, it is difficult to determine the phase of the data received by the DDR physical layer and the internal clock. This phase includes the phase of the integer clock cycle and the fractional clock cycle.

[0003] The processing method in the prior art is to calculate the integer clock delay of the read data loop by delaying the read data by multiple beats. Because the read data is a signal with a large bit width, the corresponding comparison logic will be greatly increased, and it will also bring loss of speed

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