Synchronous circuit and synchronous method based on DDR read data integer clock periods

Abstract

The invention discloses a synchronous circuit and a synchronous method based on DDR read data integer clock periods. The synchronous circuit comprises a physical layer calibration circuit and a read data effective enabling generation circuit which are connected with each other, the physical layer calibration circuit is used for performing delay multi-beat enabling comparison on the DDR read data and reference data to obtain a comparison result; and the read data effective enabling generation circuit is used for determining the integer clock period of DDR read data reaching the DDR physical layer according to the comparison result, delaying the effective enabling of the DDR read data by the determined integer clock period, and realizing the integer clock period synchronization of the DDR read data. The integer clock period of DDR read data reaching a DDR physical layer is determined by delaying multi-beat enable comparison signals, the data is effectively enabled to be delayed by the corresponding integer clock period, and integer clock period synchronization of the DDR read data is realized.

Description

technical field [0001] The invention relates to the technical field of DDR, in particular to a synchronous circuit and a synchronous method based on an integer clock cycle of DDR read data. Background technique [0002] According to the DDR protocol, after the DDR controller issues a read command, after several DDR clock cycles, the DDR particles will return DQS and DQ, and the physical layer of the controller needs to process the received data (DQ) to the internal clock of the controller. On the domain, it is dfi_rddata on the physical layer interface, and the corresponding effective control is dfi_rddata_valid. Due to the uncertainty of the connection delay between the IO (input and output port) and the board level, it is difficult to determine the phase of the data received by the DDR physical layer and the internal clock. This phase includes the phase of the integer clock cycle and the fractional clock cycle. [0003] The processing method in the prior art is to calcula...

AI Technical Summary

Problems solved by technology

Due to the uncertainty of the connection delay between the IO (input and output port) and the board level, it is difficult to determine the phase of the data received by the DDR physical layer and the internal clock. This phase includes the phase of the integer clock cycle and the fractional clock cycle.

[0003] The processing method in the prior art is to calculate the integer clock delay of the read data loop by delaying the read data by multiple beats. Because the read data is a signal with a large bit width, the corresponding comparison logic will be greatly increased, and it will also bring loss of speed

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