Parallel implementation device and method for constant setup time digital AGC loop

Abstract

The invention discloses a parallel implementation device and method for a constant setup time digital AGC loop, and the device comprises a serial-to-parallel module which is used for dividing a high-speed digital signal data flow into parallel low-speed digital signal data flows; an AGC calculation module which is used for calculating a gain factor corresponding to the low-speed digital signal data flow; an AGC application module which is used for performing AGC processing on the low-speed digital signal data flow according to the gain factor; and a parallel-to-serial module which is used for combining the low-speed digital signal data stream processed by the AGC into a high-speed digital signal data stream processed by the AGC. According to the invention, the requirement of reducing the clock frequency is met while the precision is ensured through parallel processing.

Description

technical field [0001] The invention relates to the technical field of electronic information, in particular to a parallel realization device and method of a digital AGC loop with constant set-up time. Background technique [0002] There are two main types of existing digital AGC processing processes: the first type is to subtract the output level from the reference level to obtain the error voltage, then integrate the error signal to generate a control voltage, and finally perform linear incremental gain adjustment according to the control voltage , so that the output voltage is stable near the reference level: the second type is based on the basic principle of the constant settling time AGC loop, using the power error detection method to obtain the error voltage, and then integrating the error voltage to generate a control voltage, and finally according to the control voltage. Linear logarithmic incremental gain adjustment to stabilize the output level near the reference l...

AI Technical Summary

Problems solved by technology

The implementation method of the first type is simple, but its settling time is related to the input signal level; the settling time of the second type is constant, but due to the need for logarithmic and exponential operations, the calculation resource consumption is relatively large

[0003] Type 2 constant settling time digital AGC loops such as figure 1 As shown, it can be seen that VGA contains exponential operations, while ED contains logarithmic operations, both of which are nonlinear operations, and the amount of calculation is relatively large. When implemented in FPGA, the cost of using the look-up table method is relatively high, and the implementation of floating point is used. Cannot handle high-speed digital signal data streams

The above-mentioned AGC processing requires the FPGA to use floating-point operations to perform logarithmic, exponential, and other operations on the high-speed digital signal data stream, which consumes a lot of resources and is complicated to implement.

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