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Statement block encapsulation method, device, electronic equipment and storage medium

A packaging method and a technology of statement blocks, which are applied in CAD circuit design, computer-aided design, electrical digital data processing, etc., can solve problems such as a large number of grammatical types and complex internal structures, so as to achieve rapid layout planning and reduce the risk of introducing errors risk effect

Active Publication Date: 2021-10-01
S2C
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, when encountering a statement block containing a compound structure, such as a statement block containing a compound structure such as interface / package / struct, it is necessary to go deep into these structures, search and analyze their syntax and signals, and these compound structures The internal structure of is extremely complex, and the number of grammar types involved is extremely large. It is necessary to build a dedicated grammar analysis library to match all grammar rules in order to ensure correct parsing

Method used

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  • Statement block encapsulation method, device, electronic equipment and storage medium
  • Statement block encapsulation method, device, electronic equipment and storage medium
  • Statement block encapsulation method, device, electronic equipment and storage medium

Examples

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example 1

[0117] Example 1: Merge operation between modules.

[0118] Suppose the current processing module is as Figure 5 The top module shown is merging the submodules and statement blocks inside the top module before merging. The top module has an input signal top_signal1 and an output signal top_signal2, and the module has an internal signal inter_signal1 and a composite structure (Interface type) instance interf1, and two instances of submodules that use interf1, as well as other signals, submodules, and statement blocks.

[0119] For example, if interf1 is not used by other submodules or statement blocks, it is only used by sub_module1 and sub_module2, and inter_signal1 is the internal transmission signal of these two modules.

[0120] Therefore, if Figure 6 As shown, according to the merge operation rules, sub_module1 and sub_module2 can be merged, that is, interf1 and inter_signal1 are taken back as internal signals, and a merged new module (namely newmodule) is created. The...

example 2

[0122] Example 2: Merge between module and block.

[0123] Suppose the current processing module is as Figure 8 The top module shown contains an always statement block (block), which uses interf1, so the statement block is a complex statement block, and sub_module1 also uses the interf1, which needs to be merged. Let's merge them together.

[0124] If interf1 is only used by this always statement block and sub_module1, the merged result can be as follows Figure 9 As shown, the result after updating to topmodule is as follows Figure 10 shown.

[0125] further, such as Figure 11-Figure 12 It is shown as a schematic illustration, that is, if interf1 is used by other submodules or statement blocks in topmodule except the always statement block and sub_module1, then this interface should be reserved in the port of the new module (that is, the combine_sub_module_new module in the figure) to complete and Further merging of other parts until all submodules or statement blocks...

example 3

[0126] Example 3: Merge between statement blocks.

[0127] The merging operation between two statement blocks is the same as the above two merging cases.

[0128] Assuming that interf1 is only used by these two alwaysblocks, the merge effect is as follows Figure 13-Figure 15 shown.

[0129] Further, if other submodules or statement blocks are used, the processing method is similar to the description in the previous example 2, that is, the port of interf1 is reserved in the new submodule for further merging with other related parts, and no further description will be given.

[0130] In some implementations, two-by-two merging may be used in the merging operation, and sequentially aggregated into a larger new module, which can improve processing efficiency.

[0131] During implementation, the collected statement items are combined, which may include:

[0132] Combining the collected statement items into pairs to form a third module;

[0133] The third module is instantiated...

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Abstract

The embodiment of this specification provides a sentence block encapsulation method, device, electronic equipment, and storage medium, which are applied in the field of electronic design automation technology, wherein the encapsulation method includes: determining a number of statement blocks to be encapsulated according to the segmentation boundaries obtained by the RTL segmentation tool; traversing each The statement block to be encapsulated, wherein the module where the statement block to be encapsulated is currently used as the current processing module; the current processing module is scanned to determine whether the current processing module contains a black box signal, and clusters according to the black box signal Submodules and statement blocks are packaged. By encapsulating the black box signal as a link, the RTL segmentation tool is suitable for encapsulating sub-modules and statement blocks under different grammatical rules, improving processing efficiency and realizing rapid layout planning.

Description

technical field [0001] The invention relates to the technical field of electronic design automation, in particular to a sentence block packaging method, device, electronic equipment and storage medium. Background technique [0002] The function of the RTL (Register Transfer Level, register conversion level circuit) segmentation tool is to divide the user's chip logic design code into several parts of code, which run on different FPGAs (Field Programmable Gate Array, Field Programmable Logic Gate Array). Among them, FPGAs communicate with each other through interconnection lines, and FPGAs can perform parallel synthesis and logic verification. Among them, the processing flow of the RTL segmentation tool is roughly: determine the segmentation boundary, encapsulate the statement block, form the graph structure, graph segmentation, and transfer the graph segmentation result back to the RTL-level language, so that the synthesis tool can perform logic synthesis, layout, etc. on ea...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/34G06F30/343G06F30/347G06F8/33
CPCG06F30/34G06F30/343G06F30/347G06F8/33
Inventor 邵中尉张吉锋
Owner S2C
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