Clock generation circuit and method of generating clock signals

Abstract

Clock generation circuit and method of generating clock signals. The clock generation circuit includes an inverter directly receiving an external clock signal and outputting an inverted external clock signal, M (where M is an integer >=1) loop circuits arranged in series, the first loop circuit receiving the inverted external clock signal, each of the N loop circuits having n (where n is an integer >=2) nodes, each of the M-1 loop circuits generating n intermediate internal clock signals, each at a corresponding one of the n nodes, wherein a frequency of the n intermediate internal clock signals is a multiple of a frequency of the external clock signal and the inverted external clock signal; and n sets of inverters, each including M-1 inverters connected in series, each of the M-1 inverters receiving a corresponding intermediate internal clock signal from a previous loop circuit and outputting a corresponding intermediate internal clock signal to a next loop circuit.

Description

technical field [0001] The invention relates to a clock generation circuit and method for generating clock signals. Background technique [0002] Figure 1A illustrates a conventional phase-locked loop, which includes a phase detector (PD) 10, a charge pump (CP) 12, a loop filter (LP) 14, a voltage-controlled oscillator (VCO) 16, one or more frequency dividers 18-1, 18-2, and / or one or more frequency dividers 20. [0003] A phase detector (PD) 10 receives an external clock signal ECLK and generates an UP or DN signal in response to a phase difference between the external clock signal ECLK and a feedback clock signal DCLK. When the phase of the external input signal ECLK is ahead of the phase of the feedback clock signal DCLK, the UP signal is activated. The DN signal is activated when the phase of ECLK lags behind that of DCLK. [0004] Charge pump (CP) 12 and / or loop filter (LP) 14 increase the level of control voltage Vc in response to an activated UP signal and decrease...

AI Technical Summary

Problems solved by technology

If the control voltage Vc includes noise, the output clock signals (CLK0-CLK270 and FCLK) contain errors, such as phase errors

Also, as mentioned above, traditional DLLs have the disadvantage of relatively long ring lock times

Images