Unlock instant, AI-driven research and patent intelligence for your innovation.

AD converter and solid-state imaging device

an analog-to-digital converter and solid-state imaging technology, applied in the field of analog-to-digital (ad) converters and solid-state imaging devices, can solve problems such as circuit expansion and cost increas

Active Publication Date: 2020-12-15
SHARP KK
View PDF10 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

Enables AD conversion without the need for a sign bit, resulting in a more compact and efficient circuit design that maintains high accuracy without the added complexity and cost of additional bits.

Problems solved by technology

This leads to circuit expansion and cost increase.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • AD converter and solid-state imaging device
  • AD converter and solid-state imaging device
  • AD converter and solid-state imaging device

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0021]Embodiments of the disclosure are described in detail below with reference to FIG. 1 through. FIG. 10B.

Configuration of Solid-State Imaging Device

[0022]FIG. 1 is a block diagram illustrating the configuration of a solid-state imaging device 1 of a first embodiment of the disclosure.

[0023]The solid-state imaging device 1 of the first embodiment includes a pixel unit 10, a vertical scanning circuit 20, a horizontal scanning circuit 30, a clamp circuit 40, and an analog-to-digital (AD) converter 50.

[0024]The pixel unit 10 includes row and columns of pixels 12 that perform photoelectric conversion. The pixels 12 arranged in the same row direction are connected to the same wiring line 22, and thus connected to the vertical scanning circuit 20 to be controlled. The pixels 12 arranged in the same column direction are connected to the same pixel signal line 32. The pixel 12 photoelectrically converts incident light into an analog signal. The analog signal is transferred to the AD conv...

second embodiment

[0107]A second embodiment of the disclosure is described with reference to FIG. 11. A counter 58a of the second embodiment is different in configuration from the counter of the first embodiment.

[0108]FIG. 11 illustrates the counter 58a of the second embodiment. In accordance with the second embodiment, the outputs Q of DFF 74a1, DFF 74a2, DFF 74a3, DFF 74a4, . . . , DFF 74aN are respectively connected to second latch units 7921, 7922, 7923, 7924, . . . , 792N, and composite gates 721, 722, 723, 724, . . . , 72N. The configuration of the second embodiment operates in a way similar to the first embodiment.

third embodiment

[0109]A third embodiment of the disclosure is described with reference to FIG. 12 and FIG. 13A and FIG. 13B. For convenience of explanation, elements having functionalities identical to those of the first embodiment are designated with the same reference numerals and the discussion thereof is omitted herein.

Configuration of Solid-State Imaging Device

[0110]FIG. 12 is a block diagram illustrating the configuration of a solid-state imaging device 1b of the third embodiment.

[0111]In accordance with the third embodiment, a counter and latch unit 56b includes at high-order bits thereof a high-order bit counter 58b as a ripple counter, a high-order bit first latch unit 591b, and a high-order bit second latch unit 592b. The counter and latch unit 56b includes low-order bits thereof a low-order bit counter 80 as a gray code counter, a low-order bit first latch unit 821, and a low-order bit second latch unit 822.

[0112]Each high-order bit first latch unit 591a on each pixel column is connected...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An AD converter includes a comparator that compares a potential of a pixel signal line with a reference potential that is a potential of a ramp waveform changing with time, a counter that stops a counting operation in response to a change in an output of the comparator, and an all-bit latch unit that holds all bits of a count value subsequent to stopping the counting operation during the second count period. The counter sets an initial value for the counting operation during the first count period to be a negative value, and prior to the counting operation during the second count period, inverts all bits of the count value subsequent to stopping the counting operation during the first count period.

Description

BACKGROUND1. Field[0001]The present disclosure relates to an analog-to-digital (AD) converter and a solid-state imaging device.2. Description of the Related Art[0002]Japanese Unexamined Patent Application Publication No. 2011-234326 discloses an AD conversion technique. In the disclosed technique, an AD conversion is performed by performing a first counting operation on a pixel reset potential, and a second counting operation on a pixel signal potential, and determining a difference between the result of the first counting operation and the result of the second counting operation.[0003]Referring to FIGS. 14A and 14B, the initial value of the first counting operation is set to be zero, and a counter that performs the first counting operation using down counting, and the second counting operation using up counting may be typically used. This counter is referred to an up-down counter. Another counter that performs the first counting operation using up counting, and the second counting ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(United States)
IPC IPC(8): H04N5/378H04N5/376H04N5/357H04N25/00
CPCH04N5/378H04N5/3575H04N5/3765H04N25/00H04N25/78H04N25/616H04N25/75H04N25/745
Inventor USHINAGA, TAKEO
Owner SHARP KK