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Neo-wafer device comprised of multiple singulated integrated circuit die

a technology of integrated circuit die and neo-wafer, which is applied in the direction of semiconductor devices, electrical equipment, semiconductor/solid-state device details, etc., can solve the problems of inability to achieve 100% die yield on a single wafer, and presently no reliable method of creating neo-wafer

Inactive Publication Date: 2006-05-04
JONATHAN STERN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Present wafer manufacturing techniques make 100% die yield on a single wafer generally unattainable.
Unfortunately, there is presently no reliable method of creating neo-wafers, particularly because of the problem of singulated die alignment on the neo-wafer.

Method used

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  • Neo-wafer device comprised of multiple singulated integrated circuit die
  • Neo-wafer device comprised of multiple singulated integrated circuit die
  • Neo-wafer device comprised of multiple singulated integrated circuit die

Examples

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Embodiment Construction

[0030] Turning now to FIG. 1, a sacrificial substrate 10, with a first wafer surface 12 and a second wafer surface 14 is provided. One or more recesses 20 are defined in first wafer surface 12 for the receiving of an integrated circuit die. Substrate 10 is preferably photo-imagable glass such as FORTURAN, available from Schott Corp., which is capable of achieving very high tolerance etch angles. In an alternative preferred embodiment, a quartz substrate may be used.

[0031] The diameter and geometry of substrate 10 should be that of the desired end wafer diameter and geometry.

[0032] Recesses 20 are provided with a length and width slightly greater than that of the die which will be incorporated into recesses 20 to minimize the quantity of organic material in the wafer after under-fill. The depth of recesses 20 is preferably slightly less than the sum of the thickness of the die and solder ball height to be incorporated into recesses 20 to allow subsequent planarization of first wafe...

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PUM

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Abstract

A neo-wafer made from integrated circuit die and methods for making a neo-wafer are disclosed. Recesses are formed on a substrate and a dielectric layer with conductive pads is created for the receiving of one or more die. Die are flip-chip bonded to the conductive pads and all voids under-filled. The neo-wafer is thinned to expose the dielectric and the conductive pads exposed, creating a neo-wafer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 10 / 701,783, now allowed, and is related to U.S. Provisional patent application Ser. No. 60 / 424,025, filed on Nov. 6, 2002, which is incorporated herein by reference and to which priority is claimed pursuant to 35 USC 119. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention generally relates to creating wafers from singulated integrated circuit die. Specifically, the invention relates to methods for creating a standard geometry “neo-wafer” from previously singulated integrated circuit die and to a neo-wafer created according to the methods. The invention is thus an enabling technology with respect to neo-wafers that contain all know good die (KGD). [0004] 2. Description of the Prior Art [0005] Microelectronic packages typically include one or more integrated circuit die formed on a semiconductor material, which as been bonded to a lead fr...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/44H01L21/301H01L21/60H01L21/68H01L23/31
CPCH01L21/6835H01L21/6836H01L24/81H01L24/96H01L2221/68327H01L2221/68377H01L2224/8121H01L2224/81815H01L2224/83102H01L2224/92125H01L2924/01013H01L2924/01033H01L2924/01082H01L2924/14H01L2924/3511H01L2224/04105H01L2924/00
Inventor JONATHAN, STERN
Owner JONATHAN STERN