Memory command scheduler and memory command scheduling method

Abstract

A memory command scheduler is provided. The memory command scheduler includes a scheduler queue receiving first and second requests for a memory access from external devices and storing the first and second requests therein; and a controller generating a command of the second request after a preset number of clock cycles from a current clock cycle and transferring the generated command to a memory, if generation of a command of the first request is possible in the current clock cycle and generation of the command of the second request is possible after the preset number of clock cycles from the current clock cycle.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from Korean Patent Application No. 10-2013-0093565, filed on Aug. 7, 2013, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.BACKGROUND

[0002] 1. Field

[0003] Apparatuses and methods consistent with exemplary embodiments relate to a memory command scheduler and a memory command scheduling method, and more particularly, to a memory command scheduler and a memory command scheduling method that uses a future prediction technology.

[0004] 2. Description of the Related Art

[0005] A DDRx (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory) device (here, x indicates an integer of two or more and depends on a type of SDRAM device) is operated by receiving a data read command and a data write command for a requested address position and an address from a memory controller and returning requested data through data bus, if the data read comm...

Examples

Embodiment Construction

[0050]Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0051]FIG. 1 is a diagram of an external interface and a memory command scheduler structure.

[0052]It is assumed that an m external devices may make a memory read or write request (where, m indicates an integer), and an arbitrating apparatus in a simple round robin or at least recently used scheme may be used. Even though a request for different data sizes is received, the requested data size is converted into a block unit. One block includes a plurality of bytes sent to a target DDRx SDRAM chip through a data bus interface within 8 bursts (4 clock cycles). Two entries are selected in a scheduler queue during each clock cycle. A first entry, which corresponds to an entry to be currently executed, is determined based on a current bank state, a parameter for the entry, and a latency time interval limit between several DDR commands specified in a DDRx specification.

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CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from Korean Patent Application No. 10-2013-0093565, filed on Aug. 7, 2013, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.BACKGROUND

[0002] 1. Field

[0003] Apparatuses and methods consistent with exemplary embodiments relate to a memory command scheduler and a memory command scheduling method, and more particularly, to a memory command scheduler and a memory command scheduling method that uses a future prediction technology.

[0004] 2. Description of the Related Art

[0005] A DDRx (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory) device (here, x indicates an integer of two or more and depends on a type of SDRAM device) is operated by receiving a data read command and a data write command for a requested address position and an address from a memory controller and returning requested data through data bus, if the data read comm...

Examples

Embodiment Construction

[0050]Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0051]FIG. 1 is a diagram of an external interface and a memory command scheduler structure.

[0052]It is assumed that an m external devices may make a memory read or write request (where, m indicates an integer), and an arbitrating apparatus in a simple round robin or at least recently used scheme may be used. Even though a request for different data sizes is received, the requested data size is converted into a block unit. One block includes a plurality of bytes sent to a target DDRx SDRAM chip through a data bus interface within 8 bursts (4 clock cycles). Two entries are selected in a scheduler queue during each clock cycle. A first entry, which corresponds to an entry to be currently executed, is determined based on a current bank state, a parameter for the entry, and a latency time interval limit between several DDR commands specified in a DDRx specification.

[0...

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