CAM-based search engine devices having index translation capability

Abstract

An integrated circuit chip includes a search engine including a content addressable memory (CAM) configured to produce CAM indices responsive to search instructions provided to the search engine. The search engine further includes an index translation circuit operatively coupled to the CAM and configured to provide translation of the CAM indices to another memory space, such as from an absolute index space associated with the CAM to a memory space associated with a database within the CAM or to a memory space of a device external to the chip, such as a command source or external SRAM.

Description

REFERENCE TO PRIORITY APPLICATION[0001]This application is a continuation-in-part (CIP) of U.S. application Ser. No. 10 / 721,036, filed Nov. 21, 2003, which is a continuation-in-part (CIP) of U.S. application Ser. No. 10 / 714,680, filed Nov. 14, 2003, which is a continuation-in-part (CIP) of U.S. application Ser. No. 10 / 698,246, filed Oct. 31, 2003, which claims priority to U.S. Provisional Application Ser. No. 60 / 516,178, filed Oct. 31, 2003, the disclosures of which are hereby incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention relates to integrated circuit devices that support search operations and, more particularly, to CAM-based search engine devices and methods of operating same.BACKGROUND OF THE INVENTION[0003]Conventional network processor units (NPU) may be interfaced to integrated IP coprocessors (IIPC) in a manner that enables both SRAMs and IIPCs to be operated on the same memory mapped bus. As illustrated by FIG. 1, a conventional IIPC 30 ma...

AI Technical Summary

Benefits of technology

[0009]According to various aspects of the present invention, an integrated circuit chip includes a CAM-based search engine with an index translation capability. Such an index translation can, for example, provide for translation from an “absolute” index in a searchable memory space of a search machine comprising one or more such search engine devices to a more useable format, such as a database relative index, a memory pointer for a memory associated with a command source, and / or a memory address in an external memory (e.g., SRAM) associated with the search machine. Such translation can reduce or eliminate instruction cycles in the command source and, thus, can increase overall system performance and / or throughput. According to additional aspects, the index translation circuit may be configurable (e.g., programmable) to provide respective different index translations for respective CAM segments in a search machine such that, for example, absolute indices can be returned for a first database, database relative indices may be returned for a second database, memory pointers may be returned for a third database, and addresses for associated data SRAM may be generated for a fourth database. Such segment-by-segment translation can provide more design flexibility for multi-level search applications, and can allow for more efficient usage of external memory, as CAM segments that are not used for associated data functions need not be allocated space in the external memory. According to additional aspects, the translation can account for varying entry sizes for databases stored in the search machine and / or for varying entry sizes in command source associated memory or external memory attached to the search machine.

[0010]According to still further aspects, index translation according to some embodiments of the present invention can provide an ability to more efficiently use memory space, such as external data SRAM, associated with a search engine device. Thus, for example, in contrast with conventional techniques wherein CAM indices are directly used to address external SRAM, index translation according to embodiments of the present invention can avoid allocating external memory space to CAM segments that do not have associated data.

Problems solved by technology

Unfortunately, such regular polling can consume a substantial amount of the bandwidth of instructions that are issued to the IIPC 30 and lead to relatively high levels of operational inefficiency when the IIPC 30 is running a large number of contexts.

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