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Semiconductor memory device and method for generating pipe-in signal thereof

a memory device and semiconductor technology, applied in the direction of information storage, static storage, digital storage, etc., can solve the problems of data not being data cannot be guaranteed to stably input to the pipe latch, read operation failure caused

Inactive Publication Date: 2011-01-04
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the time T2 is so short that stably inputting data D1 to a pipe latch cannot be guaranteed.
In case of generating a pipe-in signal using a conventional method, data cannot be stably input to a pipe lath when a PVT condition, etc. inside a chip changes.
Since a fact that data is not stably input to a pipe latch means that a memory device outputs false data consequently, a read operation failure is caused.

Method used

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  • Semiconductor memory device and method for generating pipe-in signal thereof
  • Semiconductor memory device and method for generating pipe-in signal thereof
  • Semiconductor memory device and method for generating pipe-in signal thereof

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Embodiment Construction

[0051]Hereinafter, a semiconductor memory device and a method for generating a pipe-in signal thereof in accordance with an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0052]FIG. 7 is a block diagram illustrating a pipe-in signal generating part of a semiconductor memory device accordance with an embodiment of the invention.

[0053]The semiconductor memory device generates pipe-in signals PINB0:3> using a preliminary signal generator 710, a delay unit 720, and a pipe-in signal generator 730.

[0054]The preliminary signal generator 710 outputs a preliminary pipe-in signal PINSTSUMB enabled whenever a read command is applied. In detail, the preliminary signal generator 710 enables a preliminary pipe-in signal PINSTSUMB when any one of main amplifier enable signals YMAE is enabled. Since one of main amplifiers is enabled when a read command is applied, one of YMAE03 (signal obtained by performing an OR-operation on YMAEs of ba...

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Abstract

A semiconductor memory device includes a preliminary signal generator configured to output a preliminary pipe-in signal enabled when a read command is applied. A delay unit is configured to delay the preliminary pipe-in signal and output the delayed preliminary pipe-in signal to match the timing of output data. A pipe-in signal generator generates a pipe-in signals that are enabled between a predetermined enable point and a next enable point of the delayed preliminary pipe-in signal output.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present invention claims priority of Korean patent application number 10-2008-0033680, filed on Apr. 11, 2008, which is incorporated by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor memory device, and more particularly, to technology that improves timing of a pipe-in signal, which is a signal conveying data to a pipe latch to allow data to be stably conveyed to the pipe latch.[0003]A semiconductor memory device can receive commands successively from the outside but does not immediately perform the successively received commands. In case of a read operation, a read CAS signal (a kind of an internal read command) should be enabled to perform the read operation. A double data rate 2 (DDR2) semiconductor memory device internally secures a time for performing successive commands by delaying an enable point of the read CAS signal. A delay time until a read CAS signal controlling a...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C7/00
CPCG11C7/1039G11C11/4076G11C11/4093G11C11/4096G11C11/407
Inventor KIM, KYOUNG-NAMCHO, HO-YOUB
Owner SK HYNIX INC