Method and apparatus for indicating multi-power rail status of integrated circuits
a technology of integrated circuits and status indicators, applied in electrical apparatus, instruments, electric digital data processing, etc., can solve problems such as adding complexity to the integrated circuit design, i/o transmitters receiving invalid data signals from the core logic, and core logic may not become stabl
Active Publication Date: 2013-03-19
ATI TECH INC
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Benefits of technology
This approach prevents the I / O transmitter from outputting unpredictable states by ensuring the core logic is stable before asserting the status signal, reducing design complexity and cost by eliminating the need for external power management modules.
Problems solved by technology
The external off-chip power management module, however, adds complexity to the integrated circuit design as each one of the power rails has to be controlled to follow the power sequence set by the external off-chip power management module.
Moreover, as the external off-chip power management module provides the status signal only based on the state of the power rails, it does not consider the possibility that, during power-up, the core logic may not become stable even though all the power rails are powered-up.
In this case, the external off-chip power management module still asserts the status signal to the I / O transmitter, and thus, causes the I / O transmitter to receive invalid data signals from the core logic before the core logic becomes stable.
Method used
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[0013]Briefly, a method and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit. The multi-power rail status indicating logic may include a synchronous assertion / asynchronous de-assertion multi-power rail status signal generator that receives the clock signal and the ...
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Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit. The multi-power rail status indicating logic may include a synchronous assertion / asynchronous de-assertion multi-power rail status signal generator that receives the clock signal and the asynchronous multi-power rail voltage stability signal, and in response to of the assertion of the asynchronous multi-power rail voltage stability signal, synchronizes the asynchronous multi-power rail voltage stability signal with the clock signal to assert the multi-power rail status signal.
Description
BACKGROUND OF THE DISCLOSURE[0001]The disclosure relates generally to methods and apparatus for indicating status of integrated circuits, and more particularly, to methods and apparatus for indicating multi-power rail status of integrated circuits.[0002]In an integrated circuit having multiple power rails and an input / output (I / O) transmitter, it is necessary to control the state of the I / O transmitter during the power-up and power-down conditions. This can be accomplished by using a status signal, also known as a “powergood” signal. When the status signal is logic high, it indicates that all power rails of the integrated circuit are fully powered up and the I / O transmitter can be controlled by core logic of the integrated circuit. When the status signal is logic low, one or more power rails in the integrated circuit are not fully powered up and the I / O transmitter can be put into a known state, such as a tri-state, a pull-up state or a pull-down state.[0003]Particularly, the timing...
Claims
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IPC IPC(8): G06F1/28
CPCG06F1/26G06F1/28
InventorFUNG, RICHARD W.LAU, RICKYNG, JU TUNG
OwnerATI TECH INC