Semiconductor device having transistor and semiconductor memory device using the same

Abstract

Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority of Korean Patent Application No. 10-2012-0141949, filed on Dec. 7, 2012, which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Field[0003]Exemplary embodiments of the present invention relate to a technology of manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of preventing off-leakage of a transistor and a semiconductor memory device using the same.[0004]2. Description of the Related Art[0005]A semiconductor device, for example, a semiconductor memory device such as a DRAM, transfers data of memory cells (MC) to bit lines BLs by supplying a specific voltage to word lines WLs for a predetermined time in an active operation mode to activate the word lines WLs and includes a bit line sense amplifier (BLSA) sensing and amplifying data of bit lines. In a read operation mode, the data amplified by the bit line sense amplifier are output ...

AI Technical Summary

Benefits of technology

[0014]An embodiment of the present invention is directed to a semiconductor device capable of preventing off-leakage of a transistor and a semiconductor memory device using the same.

Problems solved by technology

However, the back bias voltage VBB supplied to the substrate cannot function as a main factor controlling the threshold voltage of the cell transistor 101 and leads to junction leakage in a source / drain of the cell transistor 101, such that the prior art has a limitation in suppressing the off-leakage.

However, when the word lines WL are supplied with negative voltage, a potential difference between the data storage unit 102 and the word lines WLs (or gates) is increased, which may lead to a gate induced drain leakage (GIDL).