Flash memory device with stable source line regardless of bit line coupling and loading effect
一种存储设备、快闪的技术,应用在信息存储、静态存储器、只读存储器等方向,能够解决芯片尺寸增加、存储单元特性降低等问题
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[0028] FIG. 5 is a schematic diagram of a flash memory device according to an embodiment of the present invention. Referring to FIG. 5, compared with the conventional memory cell array block 300 of FIG. 3, in the memory cell array block 300 of FIG. The cell array block 500 includes selection transistors QS51 to QS54 having the same structure as memory cell transistors Q1 to Q16. In other words, memory cell transistors Q1 to Q16 and selection transistors QS51 to QS54 are both in the form of split gate transistors as figure 1 type shown. Memory cell transistors Q1 to Q16 are "off" cells that can be selectively programmed, or "on" cells that are not programmed, while selection transistors QS51 to QS54 are "on" cells that are not programmed. In this structure, the source line discharge signal SL_DIS is inverted by the inverter INV1 and sent to the discharge line SDL1.
[0029] In this case, in the read and erase modes, a voltage of 0V is applied to the discharge line SDL1 servi...
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