Atoll static release device

Abstract

The invention discloses an atoll type electrostatic discharge device for improving the back bias electrostatic damage resistance capability of light tester grains and increasing the electrostatic charge release patches to improve the grain back bias electrostatic damage resistance capability. The electrostatic release paths increased around the light tester grain are a P type metal layer, a resistance reduction area, a P type semiconductor area, an i type light absorption layer, a N type buffering layer, a N type base plate and a N type metal layer. Leading most of the electrostatic charges to release around the grains can avoid most of the electrostatic charges centered among and through the grains and cause grain damage and improve the grain back bias electrostatic damage resistance capability.

Description

technical field [0001] The invention relates to an atoll-type electrostatic discharge device that enhances the ability of a photodetector chip to resist reverse bias electrostatic damage. A P-type metal layer, a resistance-reducing region, and a P-type semiconductor region are arranged around the photodetector chip, and the Most of the static electricity is dispersed and released around the photodetector chip to avoid most of the static electricity concentrated in the middle of the chip, so as to enhance the anti-static damage effect of the chip, and the photodetector chip does not change the process steps , so the manufacturing cost will not be increased, which is in fact fully in line with industrial utilization. Background technique [0002] Press, the chip of conventional photodetector (see figure 1 and figure 2 ), the chip is mainly composed of P-type metal layer 1, light-receiving area 2, dielectric layer 3, N - Type semiconductor layer 4, P-type semiconductor regi...

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Problems solved by technology

[0002] Press, the chip of conventional photodetector (see figure 1 and figure 2 ), the chip is mainly composed of P-type metal layer 1, light-receiving area 2, dielectric layer 3, N - Type semiconductor layer 4, P-type semiconductor region 41, i-type light absorbing layer 5, N-type buffer layer 6, N-type substrate 7, and N-type metal layer 8: Among them, when there is a large amount of static electricity on the chip surface, a large amount of static electricity runs through The middle area of ​​the chip will cause damage to the chip. Apply reverse bias static electricity to simulate a large amount of static electricity passing through the chip, and apply negative static charges to the uppermost P-type metal layer 1 and the grounded bottom N-type metal layer 8. At this time, it is a reverse bias voltage. state, the negative electrostatic charge can only be concentrated in the middle area of ​​the chip and released, so that a large amount of negative static electricity penetrates through the middle area of ​​the chip, causing damage to the chip, so the ability to resist reverse bias electrostatic damage is not strong

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