SoC software-hardware partition method based on discrete Hopfield neural network

Abstract

This invention relates to one SoC software and hardware division method based on discrete Hopfield neutral network, which comprises the following steps: adopting pattern description method to divide the software and hardware problem into one detail combination optimization problem to introduce SoC division problem new module; then according to the division property, re-defining discrete Hopfield neural network element, energy function, operation equation and parameters; dividing the discrete Hopfield network as division formula on SoC chip functions.

Description

Technical field [0001] The invention relates to the technical field of software / hardware collaborative design of SoC chips and neural network algorithms, in particular to a SoC software / hardware division method based on a discrete Hopfield neural network. Background technique [0002] SoC (System-on-a-Chip), referred to as system-on-a-chip or system chip, as a new form of embedded system, is usually implemented in an IC (Integrated Chip integrated circuit chip) to complete the functions of a single computer system. hardware integrated circuits and embedded software. Compared with traditional embedded systems, SoC has many obvious advantages, such as small size, low power consumption, high reliability, and higher cost performance, etc. The disadvantages are increased complexity, high design costs, and long development cycles, which completely change the The overall design framework of the previous whole machine system is established. SoC is usually a customized IC, which ge...

AI Technical Summary

Problems solved by technology

However, due to the complexity of the SoC system, it is difficult to model and solve problems in terms of SoC modeling, constraint conditions and multi-objective refinement, optimization algorithm design, partition result evaluation, and system structure. Guarantee that the partition result is optimal, or suboptimal

Relevant research has progressed slowly in recent years, and has only been initially applied in some EDA tools

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