Memory control device

A control device and memory technology, applied in static memory, memory system, digital memory information, etc., can solve the problems of increased peak bandwidth, larger refresh bandwidth, high peak bandwidth, etc. The effect of peak bandwidth

Inactive Publication Date: 2008-07-16
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] For constant refresh, when the access to each functional module becomes a peak value, the refresh bandwidth will be directly congested, so the peak bandwidth to be compensated increases
[0012] On the other hand, intensive refreshing does not cause the problems of constant refreshing, but it needs to execute all the necessary refreshing times in a short time period when the access frequency decreases, so the bandwidth of refreshing in the time period of concentrated refreshing increases.
At this time, when using a large-capacity memory that requires a large number of refresh times, the refresh bandwidth will greatly exceed the occupied bandwidth that is reduced due to the decline in access frequency. On the contrary, it will sometimes result in a higher peak bandwidth.

Method used

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Embodiment approach 1

[0028] A memory control device according to Embodiment 1 of the present invention will be described with reference to FIG. 1 .

[0029] FIG. 1 is a configuration diagram showing a memory control device 1000 according to Embodiment 1 of the present invention.

[0030] In the memory control device 1000 shown in FIG. 1 , the memory access control circuit 100 controls accesses from a plurality of requesters to the memory that needs to be refreshed, is connected to the external memory 10 that needs to be refreshed, and also It is respectively connected to the first requester 20 and the second requester 21 that make an access request to the external memory 10 .

[0031] In addition, the memory access control circuit 100 has a constant refresh requester 30 including a constant refresh frequency register 50 and a constant refresh cycle counter 90, a first collective refresh frequency register 60 and a first collective refresh cycle counter. The first collective refresh requester 40 o...

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Abstract

The present invention provides a memory control device, which can smooth the peak bandwidth of memory access by properly dividing the bandwidth required by the refresh operation, so that the required refresh operation can be completed through a lower peak bandwidth. A constant refresh request circuit that always performs a refresh request at a constant rate and a first collective refresh request circuit and a second collective refresh request circuit respectively corresponding to the first requester and the second requester operate in parallel, wherein the first The collective refresh request circuit and the second collective refresh request circuit collectively issue refreshes during periods when the refresh request issue conditions are satisfied, such as when the memory access bandwidth decreases.

Description

technical field [0001] The invention relates to a memory control device, in particular to a memory access control circuit for controlling memory that needs to be refreshed. Background technique [0002] In recent system LSIs, a plurality of functions are often concentrated in one chip. At this time, in order to reduce system cost, reduce power consumption, etc., an integrated memory architecture in which memories inherent in each functional block are integrated is often adopted. [0003] In the integrated memory architecture, it needs to be satisfied that the sum of the peak bandwidths required by each functional module for all the functional modules is within the specified peak bandwidth. Moreover, when the sum of the peak bandwidths is large, in order to cope with this, it is necessary to increase the memory bus width, or increase the operating frequency of the memory, etc., resulting in the problem of obliterating the advantages of the integrated memory architecture, so ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/406G06F12/06G06F12/00
CPCG06F13/1636G11C11/406G11C2211/4061
Inventor 富田泰之
Owner PANASONIC CORP
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