Method of forming micro pattern of semiconductor device
A semiconductor and micro-patterning technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as increasing process steps and increasing device costs
Inactive Publication Date: 2008-10-22
SK HYNIX INC
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Problems solved by technology
These process methods not only increase the overall process steps, but also increase the cost of mass-produced devices
Method used
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Embodiment Construction
[0019] Specific embodiments according to the present invention will be explained with reference to the drawings.
[0020] The semiconductor device according to the first embodiment of the present invention will be described below.
[0021] Reference Figure 1A , An etching target layer 102 is formed on the semiconductor substrate 100. The etching target layer 102 can be any layer that requires a micro pattern (for example, an insulating layer, a conductive layer, an interlayer insulating layer, etc.). A hard mask layer 104 is formed on the etching target layer 102. The hard mask layer 104 may have a stack structure of a carbon layer 104a formed by a spin coating method and a bottom anti-reflective coating (BARC) 104b containing silicon (Si), or an amorphous carbon layer 104a and silicon oxynitride (SiON) Stacked structure of layer 104b.
[0022] A first auxiliary pattern 106 is formed on the hard mask layer 104. The first auxiliary pattern 106 may be made of a photoresist film. Th...
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A method for forming a micro-pattern of a semiconductor device is provided, comprising the steps of forming an etching destination layer on a substrate, forming a rigid mask layer on the etching destination layer, forming a first assisted pattern on the etching destination layer, to define a plurality of structures separated to each other, injecting silicon into the first assisted pattern to from a silylanized first assisted pattern, forming an insulating layer to define spacing between two adjacent silylanized first assisted patterns on the rigid mask layer and the silylanized first assisted pattern, forming a second assisted pattern on the insulating layer at the defined spacing between two silylanized first assisted patterns, etching the insulating in the following way that the insulating layer part arranged between the silylanized first assisted pattern and the second assisted pattern is removed, while the insulating layer part arranged below the second assisted pattern is not removed in the etching insulating layer, etching the rigid mask layer to define a rigid mask pattern by the silylanized first assisted pattern and the second assisted pattern as etching masks, etching the etching destination layer by the rigid mask pattern, to obtain destination micro-pattern.
Description
[0001] Cross references to related applications [0002] This application claims the priority of Korean Patent Application 10-2007-038748 filed on April 20, 2007, the entire contents of which are incorporated herein by reference. Technical field [0003] The present invention relates to a semiconductor device, and more particularly to a method of forming a micro pattern in a semiconductor device with a resolution smaller than that of a photolithography process. Background technique [0004] As the degree of integration of semiconductor devices increases, the size of the minimum line width gradually shrinks. However, the development of exposure equipment to achieve the required micro-line width has been unable to meet the requirements for higher integration. In particular, in the case of forming a silicon (Si)-containing photoresist pattern by using a silicon (Si)-containing photoresist film by implementing a conventional exposure and development process, the resolution capability ...
Claims
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IPC IPC(8): H01L21/00H01L21/02H01L21/027H01L21/033H01L21/311H01L21/3213H01L21/82
CPCH01L21/28123H01L21/0273H01L21/0337H01L21/0338H01L21/31144H01L21/32139G03F7/265
Inventor 郑宇荣
Owner SK HYNIX INC