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Integrated circuit testing method and related circuit thereof

一种集成电路、测试方法的技术，应用在电子电路测试、测量电、测量装置等方向，能够解决接点138浪费、接点以及接脚浪费、长测试时间等问题

Inactive Publication Date: 2009-03-18
ALI CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Generally speaking, a chip can have many different packages, and the number of scan chains is determined by the package with the fewest pins. Therefore, taking the package 100 shown in FIG. 1 as the package with the fewest pins as an example, nine unused contacts 138 are wasted and cannot be used to generate scan chains
On average, each scan chain shown in FIG. 1 must have more flip-flops, so many contacts and Pins are wasted resulting in longer test times

Method used

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  • Integrated circuit testing method and related circuit thereof
  • Integrated circuit testing method and related circuit thereof
  • Integrated circuit testing method and related circuit thereof

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Embodiment Construction

[0017] Please refer to FIG. 2 , which is a (functional) schematic diagram of chip contacts and their package pins. As shown in the figure, a package (body) 200 includes a chip 230 and a plurality of pins. The pins of these packages 200 include: three pins 212 for receiving control signals; six pins 212 for receiving scan input signals; six pins 216 used as scan output terminals; and a specific pin 218 used to receive a mode selection signal MODE_SEL.

[0018] The chip 230 includes a plurality of contacts and a plurality of selection units 300; wherein, the plurality of contacts include: three contacts 232 for receiving control signals; ten contacts 234 for receiving scan input signals; Ten contacts 236 for output terminals; and a specific contact 238 for receiving a mode selection signal MODE_SEL.

[0019] Each pin in the package 200 is connected to a corresponding contact in the chip 230 , and each scan-in contact 234 in the chip 230 is connected to a corresponding scan-out ...

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Abstract

An integrated circuit testing method includes: respectively connecting a plurality of pads in a chip to generate a plurality of scan chains, wherein each scan chain connects two pads and at least one flip-flop in the chip; providing at least a selecting unit, wherein the selecting unit determines a mode according to a plurality of available scan chains after the chip is packaged; and determining a target scan chain to be connected with a target flip-flop corresponding to the selecting unit according to the mode determined by the selecting unit.

Description

technical field [0001] The invention relates to testing an integrated circuit, in particular to an integrated circuit testing method using different scan chains in different testing stages and related circuits. Background technique [0002] In order to test an integrated circuit for faults generated during the manufacturing process, scan chains are generally used to test the integrated circuit. Each scan chain connects two pads and at least one flip-flop in the chip, and the test time of the scan chain is proportional to the length of the scan chain, wherein the length of the scan chain represents the number of flip-flops on the scan chain . Therefore, the number of flip-flops on this scan chain needs to be reduced to save test time. [0003] Under the same chip design, the number of flip-flops in the chip is fixed. Therefore, in order to save test time, the number of scan chains in the chip should be as large as possible. The larger the number of scan chains, the average ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/3185
CPCG01R31/318558
Inventor 江忠信
Owner ALI CORP