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Semiconductor device

A semiconductor and device technology, applied in the field of semiconductor devices, can solve the problem of reducing the improvement effect of delay characteristics, and achieve the effect of improving delay characteristics

Inactive Publication Date: 2010-06-09
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the transistor size increases, the parasitic capacitance of the transistor size increases, which reduces the improvement effect of delay characteristics

Method used

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  • Semiconductor device
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Embodiment Construction

[0021] Hereinafter, a semiconductor device including a circuit such as the level conversion circuit of the present invention will be described with reference to the drawings.

[0022] refer to figure 1 , the level conversion circuit of the semiconductor device of the present invention includes a VDD1 region 10 and a VDD2 region 20 . The VDD1 area 10 is for circuits on the low-voltage operation side, and the VDD2 area 20 is for circuits on the high-voltage operation side. Here, the power supply on the VDD1 area 10 side is defined as VDD1. Also, the power supply on the VDD2 area 20 side is defined as VDD2. In such a case, the voltage of VDD2 is higher than the voltage of VDD1.

[0023] The VDD1 region 10 includes an inverter 11 . The inverter 11 is a circuit that outputs a logic voltage level on the output side by inverting the logic voltage level on the input side. For example, if the voltage on the input side is a high-level voltage (H) (High), the inverter 11 logically s...

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Abstract

A semiconductor device includes an inductor configured to supply a current to a first node based on a higher voltage region power supply voltage. A first switch is configured to selectively supply a current from the first node into a third node based on a voltage on a second node; a second switch is configured to selectively supply a current from the first node into the second node based on a voltage of the third node; a third switch is configured to supply the current from the third node into a ground terminal based on a lower voltage region input logic level; and a fourth switch is configured to be turned ON / OFF alternately with the third switch to supply the current from the second node to the ground terminal.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a level conversion circuit using two mutually different power supply groups. Background technique [0002] As a technique related to a conventional level conversion circuit, Japanese Patent Application Publication (JP-A-Heisei, 5-284005: First Conventional Example) is known. In a conventional level conversion circuit as shown in the first conventional example, an N-channel transistor is required to operate at a low voltage. Therefore, in order to increase the current performance with a low Vgs, the size of the N-channel MOS transistor (NMOS) should be made as large as possible, and the size of the P-channel MOS transistor (PMOS) should be made as small as possible. [0003] In such a case, due to the lack of performance of the P-channel transistor, especially as the voltage difference between the high voltage side and the low voltage sid...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/0175H03K19/0185
CPCH03K3/356113H03K5/07H03K3/012
Inventor 福井正
Owner NEC ELECTRONICS CORP