Liquid crystal display panel

Abstract

The invention provides a liquid crystal display panel, which comprises a plurality of basic arrangement units, wherein each basic arrangement comprises six lines, wherein the first line includes four first color sub-pixels, the second line includes four second color sub-pixels, the third line includes four third color sub-pixels, the fourth line includes four fourth color sub-pixels, the fifth line includes four fifth color sub-pixels and the sixth line includes four sixth color sub-pixels. The invention has the advantages that: by changing the arrangement way of a pixel array and using a line reversal drive way the stability of common voltage electrical level is maintained. In addition, grid pulses output by an upper grid line and a lower grid line adjacent to each other of the sub-pixel are not overlapped through the connection treatment of a wiring area so as to maintain a normal display picture.

Description

technical field [0001] The invention relates to a liquid crystal display panel, in particular to a liquid crystal display panel integrating a grid driving circuit. Background technique [0002] Generally speaking, a liquid crystal display panel includes a plurality of gate lines connected to a gate driver, and a plurality of data lines connected to a data driver, or called a source driver. (source driver). In order to effectively reduce the number of data lines and reduce manufacturing costs. Therefore, a liquid crystal display panel with tri-gate pixel arrangement is proposed. That is to say, the red, green, blue (R, G, B) sub-pixels (sub-pixels) in each pixel are arranged along the direction of the data line, so that a complete display screen needs 3 times the original grid. The number of drivers, but can be matched with the integration of the gate driver on the LCD panel, so the overall production cost can be reduced. [0003] Please refer to Figure 1A , which is a s...

AI Technical Summary

Problems solved by technology

And this operation mode will cause a data writing time (t2) between the gate pulses output by the two adjacent gate lines of the sub-pixel to overlap, so when the data is written, the adjacent gate lines It will affect the voltage of the sub-pixel through the parasitic capacitance between the sub-pixel and the gate line, which will make the display screen abnormal

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