Method for improving loading effect of grid-electrode side wall growth of chip

Abstract

The invention discloses a method for improving a loading effect of grid-electrode side wall growth of a chip. The method comprises the following steps: designing a group of filling patterns, and after a grid layer of the chip is grown, choosing one of the group of filling patterns to distribute the grid on an area, in which the pattern density and the loading effect of following grid-electrode side wall growth are needed to be adjusted, on the grid layer, thereby enabling the pattern density of the chip to be a target pattern density and enabling the loading effect of the grid-electrode side wall growth of the chip to be a target loading effect. The method can be used for optimizing the homogeneity of chemical mechanical grinding and the macro loading of etching in the chip and simultaneously improving the phenomenon of unbalanced load of a local surface of the grid electrode in the growing process of a grid-electrode side wall film.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a method for improving the load effect of chip grid side wall growth. Background technique [0002] In the prior art, when the gate sidewall layer, such as the silicon nitride sidewall layer of the polysilicon gate, is grown, the design of the existing chip makes the loading effect of each part of the chip different. Such as figure 2 As shown, the reason for the different local loading effects is that the film growth of the gate spacer layer not only occurs on the top 1 of the polysilicon and between the polysilicon 2, but also simultaneously occurs on the side 3 of the polysilicon, that is, it is integrated with the polysilicon related to surface area. [0003] In the prior art, the design of the polysilicon gate layer is mainly based on the consideration of the pattern density, which is of great significance for improving the uniformity of che...

AI Technical Summary

Problems solved by technology

However, the prior art does not take into account the fact that the local surface area of ​​the polysilicon gate causes different loads during the film growth of the subsequent gate spacer layer, which will result in different loads on each local surface on the chip after the gate spacer is grown. balance, so that the subsequent etching process for forming the gate sidewall has the problem of unbalanced etching

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